A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

Lin, Chin‐Yu; Wei, Yen-Hsin; Lee, Tai-Cheng

doi:10.1109/jssc.2018.2793535

Cited by 64 publications

(35 citation statements)

References 9 publications

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“…The offset mismatch does not vary with the input signal frequency. It can be evaluated from the noise data of each sub-ADC and rectified by the subtraction operation without difficulty [32]. The M-channel wideband TIADC model with channel mismatches is shown in Fig.…”

Section: Derivation Of Lfm Signal Pulse Compression Carrying Tiadc Chmentioning

confidence: 99%

“…In TIADC systems, channel mismatches seriously degrade the signalto-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) [18,19,20,21,22,23,24,25,26,27,28,29]. In published literature, studies of TIADC are based on the effects of channel mismatches on the spectrum or dynamic performance such as SNDR and SFDR [14,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32]. Under the condition of large bandwidth, it is impossible to eliminate channel mismatches completely.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of TIADC channel mismatch effects on high-resolution range profile

Xiao

Zhang

2020

IEICE Electron. Express

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The wideband echo signals of the imaging radar can be processed by pulse compression to obtain high-resolution range profile (HRRP). The resolution of HRRP is proportional to the signal bandwidth. The pursuit of high resolution makes the bandwidth of radar transmitting signal larger and larger. And the corresponding sampling rate of receiver becomes so high that analog-to-digital conversion cannot be realized by a single chip correctly. Time-interleaved analog-to-digital converter (TIADC) technique increases sampling rate of radar receiver, but channel mismatches are brought in. Channel mismatches significantly deteriorate the dynamic performance of radar receiver. Effects of channel mismatch on SNR, SNDR and SFDR are studied in previous literatures. Derivation and simulation of TIADC channel mismatch effecting on HRRP are performed in this letter. Simulation results show that without considering the amplitude-frequency distortion and phase-frequency distortions of the radar system, when the gain mismatch is less than 0.7 times and the clock mismatch is less than 0.25 rad, the influence of the channel mismatch on the HRRP can be neglected. The results provide a reference for system design and compensation method, which are useful for the designer to determine whether complex channel mismatch calibration is necessary under specific application background.

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Section: Derivation Of Lfm Signal Pulse Compression Carrying Tiadc Chmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of TIADC channel mismatch effects on high-resolution range profile

Xiao

Zhang

2020

IEICE Electron. Express

View full text Add to dashboard Cite

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“…Since the offset and gain mismatches are static errors, their corrections are straightforward and simple, and they can be estimated by giving DC reference voltage to the input of the ADC during the calibration period [26]. In contrast, the time skew mismatch is relatively difficult to correct because the skew-induced error is dependent on signal content [6,27].…”

Section: Self-calibration Techniquementioning

confidence: 99%

“…As for successive approximation register (SAR) ADC, which has superior energy efficiency, its speed potential usually requires very advanced technology (e.g. 40 nm or even smaller) because of its primarily digital nature [4][5][6]. Moreover, the sampling rate of a single SAR ADC is still not very high, so the time-interleaved architecture is often preferred for overcoming the speed limitation.…”

Section: Introductionmentioning

confidence: 99%

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

et al. 2019

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A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

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“…High-speed analog-to-digital converters (ADCs) with a moderate resolution of 6-8 bits while maintaining excellent power efficiency for longer battery life are highly demanded for applications such as 802.11 ad (WiGig) radio architectures and the next-generation mobile communication system (5G) [1]. Compared with flash and pipeline ADC, successive approximation register (SAR) ADC has superior energy efficiency and is more suitable for the aggressive downscaling of technology because of its primarily digital nature [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

et al. 2019

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This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

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A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

Cited by 64 publications

References 9 publications

Analysis of TIADC channel mismatch effects on high-resolution range profile

Analysis of TIADC channel mismatch effects on high-resolution range profile

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

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