A 10-bit 40MS/s low power SHA-less pipelined ADC for system-on-chip digital TV application

Shylu, D. S.; Moni, D. Jackuline; Pearlin, T. Renita

doi:10.1109/icdcsyst.2016.7570596

Cited by 5 publications

(6 citation statements)

References 15 publications

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“…This op-amp design includes the design of differential inputs, differential outputs, folded cascode bias circuits with common mode feedback (CMFB) and gain boosting amplifiers. [31][32][33] The feedback factor β is given by:…”

Section: Fig 4 Cascoded Gain Stage With Gain Boosting Techniquementioning

confidence: 99%

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

Sam

Moni

Paul

et al. 2021

Silicon

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This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp-p,diff input signal while consuming only 7.3mW power from 1.8V supply.

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Section: Fig 4 Cascoded Gain Stage With Gain Boosting Techniquementioning

confidence: 99%

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

Sam

Moni

Paul

et al. 2021

Silicon

Self Cite

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“…Two comparators are used in the pipelined stage and the sub-ADC used in this work is 1.5 bits per stage. To obtain the threshold voltage of −V ref /4 the positions of threshold voltages are switched (Shylu et al , 2016a, 2016b). The average power consumption is 6 µW per comparator.…”

Section: Power Reduction and Speed Enhancement Techniquesmentioning

confidence: 99%

“…During the sampling phase, the op-amp is in the reset condition. The op-amp is mainly active in the amplification phase (Andrew et al , 2013; Shylu et al , 2016a, 2016b). The main idea behind the switched op-amp sharing technique is the replacement of switches using op-amps and the usage of op-amps in both phases (Kuo et al , 2010).…”

Section: Power Reduction and Speed Enhancement Techniquesmentioning

confidence: 99%

“…The sampling network in the next succeeding stage samples this residue signal (V out ). Because of this reason, the op-amp is made active in all the phases (Shylu et al , 2016a, 2016b). The transfer function of the pipelined ADC is represented as:…”

Section: Power Reduction and Speed Enhancement Techniquesmentioning

confidence: 99%

“…In switched op-amp technique, the amplifier is used in both stages and usage of the amplifier in each stage is optimized. The op-amp sharing technique is the prominent technique for reducing power consumption to a greater extent (Shylu et al , 2016a, 2016b). The parallel sampling technique processes a full-scale large input signal range and the size of the sampling capacitors are reduced (Yu Lin et al , 2012).…”

Section: Introductionmentioning

confidence: 99%

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A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Sam

Paul

2021

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Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

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A novel Sub-Radix-2 technique for low power Time – Interleaved SAR ADC

Atchaya,

Sam,

Paul

et al. 2023

Preprint

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A new architecture for a low-power successive approximation register analog to digital converter (SAR ADC) is presented in this paper. In addition to the channel, there is a fast coarse SAR quantizer and a 2-way time-interleaved (TI) fine SAR ADC interleaved with the channel. The SAR ADC is used to find all the quantization levels by converting the analog input signal into digital output. Comparing interleaved SAR ADCs to pipeline ADCs, interleaved SAR ADCs can help reduce the overall cost, power consumption, and size of an equivalent system. The proposed ADC power consumption is gradually reduced by optimizing the transfer sequence using the subradix-2 technique .The optimized subradix-2 scheme is compared with the conventional scheme in TI and single-channel and TI states. Simulated results show that the proposed ADC consumes 3.85 mW of power consumption in 45 nm CMOS, which demonstrates its efficiency at 1V supply voltage.

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A 10-bit 40MS/s low power SHA-less pipelined ADC for system-on-chip digital TV application

Cited by 5 publications

References 15 publications

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

A novel Sub-Radix-2 technique for low power Time – Interleaved SAR ADC

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