A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Chung, Hayun; Ishikuro, Hiroki; Kuroda, Tadahiro

doi:10.1109/jssc.2012.2184640

Cited by 66 publications

(27 citation statements)

References 22 publications

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“…These articles show a TDC operating at up to 610-fs resolution with a 5-ns range (or 1.21-ps resolution with a 328-us range) using a switched capacitor array (and a VCO) for the 328-us range) for the DTC, which is explained in more detail in [30]. Building on this, Chung et al [31] propose unrolling the SA loop in order to increase the sample rates. Using 65-nm CMOS (compared with 350 nm in [29]), 80 MS/s was achieved, compared to 5 MS/s in [29].…”

Section: B Successive Approximation Tdcmentioning

confidence: 99%

“…Using 65-nm CMOS (compared with 350 nm in [29]), 80 MS/s was achieved, compared to 5 MS/s in [29]. However, due to the inferior switchedcapacitor implementation, Chung et al [31] only managed a 9.77-ps resolution. Jiang et al [32] present a technique one might call a linear SA TDC, which linearly increases the delay until the two signals align.…”

Section: B Successive Approximation Tdcmentioning

confidence: 99%

See 1 more Smart Citation

A Review of New Time-to-Digital Conversion Techniques

Tancock

Arabul

Dahnoun

2019

IEEE Trans. Instrum. Meas.

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Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.

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Section: B Successive Approximation Tdcmentioning

confidence: 99%

Section: B Successive Approximation Tdcmentioning

confidence: 99%

A Review of New Time-to-Digital Conversion Techniques

Tancock

Arabul

Dahnoun

2019

IEEE Trans. Instrum. Meas.

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“…Thus far, many TDCs have been presented which have been trying to show high signal-to-noise ratio (SNR), resolution, bandwidth, and linearity. In this way, various TDC architectures such as time-interleaved, pipelined, flash, Successive approximation register (SAR) and cyclic architectures have been introduced [8][9][10][11][12][13][14]. Since these architectures operate in Nyquist rate, they are ineligible to achieve important parameters of performance such as dynamic range and resolution higher than that of their oversampling counterparts.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

et al. 2019

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An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved.

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“…The TDSA is previously used in [47] and [48]. In [47], two loops with digital-to-time converters are used to adjust the delay between the two time instances until the difference is solved.…”

Section: Time Domain Successive Approximationmentioning

confidence: 99%

“…In order to reduce long conversion latency in CTDSA due to adjusting the delay in both signals and the need for two DTCs, [48] proposes another search based scheme in which the delay adjustment is done only on one of the inputs, depending on the lead or lag, while a fixed delay, equal to half of the delay adjustment, is added to the other input regardless of phase lead or lag. In this scheme, called Decision-Select Successive Approximation, although the long latency of decision making is improved, due to use of many delay elements in the chain, complicated calibration scheme is required for accurate decision making.…”

Section: Time Domain Successive Approximationmentioning

confidence: 99%

Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

Amid¹

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ii Abstract The limitations and the effect of the performance of the binary phase detector on the overall performance of the digital phase-locked loop is the main focus of the research presented in this proposal. In the first part of the research, the gain limitation of the binary phase detector on the performance of the digital Bang-Bang phase-locked loop is investigated. Then to validate the concept that is explained and to improve the performance of the digital loop under the gain limitation, two schemes are explored and explained. In one scheme a random bit-stream which is noise-shaped using a software defined Σ∆ modulator is used to dither the reference and improve the performance and in the second scheme a Time-Amplifier is used to improve the digital loop performance by preventing the phase detector from operating in metastable region.The second part of the research focuses on a novel multi-bit phase detector for high-speed applications where high-resolution performance is needed and the jitter budget is stringent. In this design a Transmission Delay Line is used to generate the delayed versions of the input clock. The performance of this phase detector is analyzed in detail using stochastic analysis.In the second multi-bit phase detector a search algorithm is used to find i the closest delayed reference to the feedback clock. This scheme provides superior performance compared to the first scheme as its performance is not affected by the mismatch of the binary phase detectors used in the first scheme. The performance of the two design are compared and example of the performance in the loop is provided.ii

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A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Cited by 66 publications

References 22 publications

A Review of New Time-to-Digital Conversion Techniques

A Review of New Time-to-Digital Conversion Techniques

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

Design, Analysis and Modeling of the Effect of the Phase Detector in Digital Phase-Locked Loops

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