A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors

Aghighi, Amin; Alameh, Abdul Hafiz; Taherzadeh-Sani, Mohammad; Nabki, Frédéric

doi:10.1109/icecs.2016.7841171

Cited by 9 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 6 shows the merged DAC A , DAC y , and the multiplier for producing the error vector, e. Current mode logic (CML) based circuits have been used to simplify the design, and also make it possible to linearly operate at very high frequencies with a low level of consumption and complexity [12][13][14][15][16]. While DAC A and multiplier are shown in the right-hand side of the schematic (Fig.…”

Section: Circuit Level Simulationsmentioning

confidence: 99%

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Aghighi

Farhang‐Boroujeny

Tajalli

2021

VLSI-SoC: Design Trends

Self Cite

View full text Add to dashboard Cite

A hybrid analog/digital signal processor has been proposed to implement energy-efficient multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov Chain Monte Carlo (MCMC) algorithm for a 4×4 MIMO system is presented. A careful partitioning between analog and digital domains has been made to to reduce system power consumption. The outputs of the proposed analog signal processing unit are being converted to digital using a lowresolution analog-to-digital converter (ADC), to deliver the signals to the digital portion of the detector system. The proposed 4×4 MCMC MIMO detector is designed in a standard 45 nm CMOS technology, that consumes 29.3 mW from 1.0 V supply. A throughput of 235.3 Mbps is achieved, while operating at 1.0 GHz clock frequency. The design occupies a 0.11 mm 2 silicon area.

show abstract

Section: Circuit Level Simulationsmentioning

confidence: 99%

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Aghighi

Farhang‐Boroujeny

Tajalli

2021

VLSI-SoC: Design Trends

Self Cite

View full text Add to dashboard Cite

show abstract

“…As V c_R increases, the source node of M 1 gets increasingly degenerated with a reduced R s1 , leading to an overall increase in the dc gain. The zero and the poles of the CTLE are given in (1). ω z1 is decided by the degeneration elements, R s1 and C s .…”

Section: Analogue Equaliser Cellmentioning

confidence: 99%

“…Introduction: Due to the demand for wide bandwidth at data rate of tens of Gbit/s, inductive peaking [1] for the analogue equalisers is commonly used in the wireline receivers. However, the passive inductors result in large area, thus making the overall solution not suitable for compact on-chip wireline solutions.…”

mentioning

confidence: 99%

0.058 mm ² 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss

et al. 2018

View full text Add to dashboard Cite

An inductorless 13 Gbit/s analogue equaliser with an additional low-frequency equalisation (LFEQ) to counter the low-frequency channel losses is presented. An active feedback topology for the proposed equaliser together with negative capacitance circuit is used to extend the bandwidth to compensate a 15 dB channel loss at Nyquist. The LFEQ improves the measured data jitter of the conventional equaliser from 0.41 to 0.12 UI, for a pseudorandom binary sequence of 2 31 − 1. The proposed prototype was implemented in 65 nm CMOS, occupying active area of merely 0.058 mm 2. It exhibits a power efficiency of 1.07 mW/Gitb/s under a supply voltage of 1.2 V and a BER < 10 −12 .

show abstract

“…However, The signal frequency-dependent insertion loss in serial link channels has become the major limiter as skin effect, dielectric loss and coupling loss existing in the communication channels, causing intersymbol interference (ISI) which is the bottleneck for high speed-rate and long distance communication. In order to maximize the channel bandwidth utilization rate and improve the performance of transmission system, equalization technologies such as decision feedback equalizer (DFE) [3,4,7,9] and continuous-time equalizer (CTLE) [2,5,6,8,10] have been utilized to compensate the non-ideal characteristic in the receiver side. The equalizer can compensate the useful frequency component in the Nyquist frequency range, and restrain ISI even with channel conditions and process-voltage-temperature variations.…”

Section: Introductionmentioning

confidence: 99%

A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard

Chen

Gong

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

A 12.5 Gbps continuous-time linear equalizer circuit (CTLE) constructed with two stage equalizer, three stages of limiting amplifier and designed in 55 nm CMOS technology for high speed serial interface of JESD204B standard is presented. Beside using degeneration RC pair to compensate low pass response of the channel and high frequency signal loss, the first equalizer also utilizes inductive shunt peaking technology to further extend the bandwidth of input signals. The proposed circuit was simulated with post layout parasitic extraction and achieves around 20 ps peak-to-peak jitter, 1.08 V voltage swing and a data rate of 12.5 Gbps through 10-inch FR-4 PCB trace with the characteristic of low equalization power consumption.

show abstract

A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors

Cited by 9 publications

References 6 publications

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

0.058 mm ² 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss

A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard

Contact Info

Product

Resources

About

A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors

Cited by 9 publications

References 6 publications

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

0.058 mm 2 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss

A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard

Contact Info

Product

Resources

About

0.058 mm ² 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss