A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

Abstract

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300 × 500 μm2. With the novel half rate period calibration clock data recovery (CDR) circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE).