A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS

Abstract

An unclocked analog decision-feedback equalizer (ADFE) is implemented in a 0.18-µm 40 GHz f t CMOS process to equalize legacy FR-4 backplane channels at 8~10-Gb/sec. The critical first feedback-loop latency requirement of the DFE is met by using a novel unclocked feedback topology and currentmode logic (CML) circuit building blocks. The circuit consists of a 4-tap linear analog feed-forward filter that cancels pre-cursor inter-symbol interference (ISI) to partially open the eye and a novel 1-tap analog tunable CML feedback filter that enables cancellation of the first post-cursor at 10-Gb/sec without the use of smaller process nodes or speculative techniques. The chip with pads occupies 1.04 mm 2 and draws 240 mA DC current from a 1.8 V supply at a typical process corner. The ADFE is used to equalize 20 inches of FR-4 backplane traces at 8-Gb/sec and 10-Gb/sec.

A reduced power, 6-tap programmable pre-emphasis circuit

“…The equalizer based on the digital circuit is discussed in this thesis. The equalizer can be linear [10,17], non-linear [18][19][20] or both [16,21]. The linear equalizer can be implemented on the transmitter side [10,22] or on the receiver side [21,23]…”

“…As pointed out in Chapter 2, the FFE can be implemented in the transmitter side or the receiver side. As at the receiver side, we do not have the clock information, most FFEs implemented at the receiver side are either an analog FFE [14,17] or a digital FFE using delay line variation between the taps [21]. The difference of the delay values increases jitter.…”