A 100 Gbps Turbo Product Code Decoder for Optical Communications

Wang, Yaqi; Lin, Jun; Wang, Zhongfeng

doi:10.1109/iccc47050.2019.9064204

Cited by 3 publications

(2 citation statements)

References 13 publications

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“…It is impractical to fully unroll the corresponding soft-decision decoders for applications which require codes with large block lengths. Thus, such turbo product decoders cannot reach as high throughput as hard-decision decoders, but in exchange provide a higher net coding gain [41].…”

Section: B Variable-rate Product Decoder (Vrpd)mentioning

confidence: 99%

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder

Jain

Fougstedt

Larsson-Edefors

2021

IEEE Trans. Circuits Syst. I

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Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38 dB at a post-FEC bit-error rate of 10 −15 . The decoder achieves throughputs in excess of 400 Gb/s, latencies below 53 ns, and energy efficiencies of 1.14 pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5 dB, but at a significant area cost.

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Section: B Variable-rate Product Decoder (Vrpd)mentioning

confidence: 99%

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder

Jain

Fougstedt

Larsson-Edefors

2021

IEEE Trans. Circuits Syst. I

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“…Taking advantage of parallel decoding, parallel concatenation structures of polar codes have also been broadly investigated [5][6][7][8], among which the product coding schemes play major roles. Due to their low-complexity and high parallelism, product coding structures have been widely used for optical communications [9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of Polar Codes via UEP Product Coding

Liang

Cai

et al. 2022

Electronics

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Aiming to improve the error correction performance of polar codes, researchers have proposed employing the product coding structure involving RS codes of different rates in the horizontal direction and the short polar codewords along the vertical direction. However, there is no efficient algorithm optimizing the rate allocation of RS codes. In order to address this problem, this paper provides an analytical formulation by maximizing the number of correctly decoded information bits. The proposed rate allocation formulation takes the channel statistics into consideration, and we further find that the number of different RS code rates could be limited to a small value. By doing so, the complexities of both the rate allocation optimization and the iterative product decoding could be reduced. Simulation results demonstrate the superiority of RS-polar product codes with the proposed rate allocation method over both additive white Gaussian noise channels and Gilbert–Elliott channels. When the inner polar codes of rate 1/2 are utilized, the optimized RS-polar product codes of low-to-medium rates significantly outperform the successive cancellation decoding of long polar codes, in the regime of a frame error rate ≥10−3.

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