A 100MHz–2GHz 12.5x sub-Nyquist rate receiver in 90nm CMOS

Yoo, Juhwan; Becker, Stephen; Loh, Matthew; Monge, Manuel; Candès, Emmanuel J.; Emami, Azita

doi:10.1109/rfic.2012.6242225

Cited by 59 publications

(40 citation statements)

References 8 publications

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“…On the hardware side, we present a fully integrated wideband CS receiver called the random-modulation preintegrator (RMPI) [9,10,12,17]. We fabricate this device with Northrop Grumman's 450 nm InP HBT bipolar process.…”

Section: Introductionmentioning

confidence: 99%

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

Yoo

Turnes

Nakamura

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-In this paper we present a complete (hardware/software) sub-Nyquist rate (×13) wideband signal acquisition chain capable of acquiring radar pulse parameters in an instantaneous bandwidth spanning 100 MHz-2.5 GHz with the equivalent of 8 ENOB digitizing performance. The approach is based on the alternative sensing-paradigm of CompressedSensing (CS). The hardware platform features a fully-integrated CS receiver architecture named the random-modulation preintegrator (RMPI) fabricated in Northrop Grumman's 450 nm InP HBT bipolar technology. The software back-end consists of a novel CS parameter recovery algorithm which extracts information about the signal without performing full timedomain signal reconstruction. This approach significantly reduces the computational overhead involved in retrieving desired information which demonstrates an avenue toward employing CS techniques in power-constrained real-time applications. The developed techniques are validated on CS samples physically measured by the fabricated RMPI and measurement results are presented. The parameter estimation algorithms are described in detail and a complete description of the physical hardware is given.

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Section: Introductionmentioning

confidence: 99%

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

Yoo

Turnes

Nakamura

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…Our D.C. coupled system is complementary to the radio frequency architectures recently reported in [17,18]. We expect that further optimization of the circuit components combined with fabrication in a state-of-the-art process will allow our system to span both ranges of operating frequencies.…”

Section: Discussionmentioning

confidence: 90%

“…From a hardware perspective, compressive sampling is desirable because the modulation of the input signal with a binary sequence is simpler and easier to implement at high sampling rates as compared with the sample and hold circuits necessary for interleaved architectures. A single chip sub-Nyquist sampling receiver architecture operating between 100 MHz and 2 GHz was recently reported in the literature [17,18].…”

Section: Analog To Information Convertermentioning

confidence: 99%

Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

2013

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Abstract:We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

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“…Unfortunately, although many works discussed the structures of AIC, only few works discussed the practical hardware implementation, e.g., [4,6,7,8,9,10,11]. [6] proposed the hardware implementation of an AIC scheme based on MWC, and [4,7] presented the hardware platforms of RMPI. For RD-AIC, [8,9,10,11] described the theory and hardware implementation; however, they only gave the simulated results.…”

Section: Introductionmentioning

confidence: 99%

A hardware implementation of random demodulation analog-to-information converter

Cui

Wang

et al. 2016

IEICE Electron. Express

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Abstract:The analog-to-information converter (AIC) based on compressed sensing samples the analog signals at sub-Nyquist rate. This paper presents a low-cost hardware implementation of AIC based on random demodulation. The realization consists of a sampling part and a transmission part, which are connected by using a FPGA chip. In the former, the input analog signal is modulated with a pseudo-random sequence, and sampled with sub-Nyquist rate to obtain low-dimensional measurements. In the latter, the measurements are transmitted with user datagram protocol to the computer. The experimental results demonstrate the effectiveness of the hardware implementation.

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A 100MHz–2GHz 12.5x sub-Nyquist rate receiver in 90nm CMOS

Cited by 59 publications

References 8 publications

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

A hardware implementation of random demodulation analog-to-information converter

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