A 10b 20mhz Two-Step Parallel ADC with Internal S/H

Abstract

EARLIER FLASH CONVERSION methods employed 1024 comparators and required large die areas and power dissipation'. The ADC to be presented uses a two-step parallel conversion method, and achieves power dissipation of 900mW in a 25mm2 chip, using 4 . 5 G l l z -f~, 3pmrule standard bipolar technology. For convrnience, sample-and-hold circuit has also been included. Applications include digital video cameras and high-definition video equipment.A block diagram of the converter is shown in Figure 1. The convertvr consists of a sample-and-hold circuit, a 6 b AD/DA subsystem which combines a 6h first ADC and a 6 b DAC, a differential amplifier (Diff.Arnp.l), a 6 b second ADC, an adder, data output latches, and a gain adjustment circuit. Analog input is first sampled-and-held, and then converted t o digital data by the first ADC, and this digital data is convrrted t o analog data by the DAC. The first ADC determines six upper bits. Dif'Arnp.1 amplifies thr, difference between actual input and DAC output. This amplifier enables the second ADC t o be relatively less precise. The analog output of Diff.Arnp.1 is fed to the second ADC which determines the lower bits. Because of errors caused in the first ADC, the output of DifS.Arnp.1 exceeds the input range of the second ADC. To correct such crrors, digitally, the input range of the second ADC is quadrupled. That is, two extra bits are produced by the secorrd ADC, which has a 6 b resolution.Linearity of the complcte converter depends on DAC accuracy and on accuracy of gain matching of DAC and srcond ADC. A segment-typc DAC is used to provide this feature. The one-step voltage o f the DAC output (11,SB for D.4C) amplificd by Diff. Arnp.1 must be equal to !4 full-scale of the second ADC, because the second ADC has two extra bits. To achieve high-accuracy gain matching, a gain adjustment circuit is uscd t o insure accuracy. The reference voltagc. of the second .4DC is supplied by an amplifier, DifJArnp.2, which is identical t o Diff.Arnp.1, and which anrplifics the voltage drop across resistor Kr; it is identical to the load rcsistor Kd of the D A C and the current generated by two segmrntcd current sourcrs of D.4C flows in it. Because Diff.Arnp.2 has diff'rrerrtial output and Kr is driven by a pair of currcnt sources, the one-step voltage of DAC output amplified 'Takernoto. T.. et al.. " A Fully Parallel 10b A/D Converter with Video Speed", IEEE J. Solid-State Circuits, Vol. SC-17, P. 1133; Dec., 1982. 'Hotta. M., Maio, K.. Yokozawa, N., Watanabe, T., Ueda, S.. " A 1 5 0 m W 8b Video-Frequency A/D Converter". IEEE J. Solid-Stale Circuils. Vol. SC-21. p. 318: April, 1986. 1 by Diff.Arnp.1 is exactly equal t o % full-scale of the second ADC.Additionally, the segmented current source of the DAC is controlled by the operational amplifier so that one-step voltage of the DAC output can be equal t o the unit voltage of the first ADC reference. This can be achieved because voltage drop a c r o s resistor Rg, which is identical t o Rd, is equal to one-step voltage of the D A G since the ...

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High-quality frame-synchronization and encryption for satellite video signal transmission

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