A 10GS/s 8b 25fJ/c-s 2850um<sup>2</sup> Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

Liu, Juzheng; Hassanpourghadi, Mohsen; Chen, Mike Shuo-Wei

doi:10.1109/isscc42614.2022.9731625

Cited by 24 publications

(7 citation statements)

References 5 publications

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“…A time-to-digital converter (TDC) can measure the time difference between two input events or pulse widths. There are many architectures for high-resolution TDCs, including a vernier-based delay chain TDC [5], a time amplifier-based TDC [6,7], and a gated-ring oscillator (GRO) TDC [8]. A purely digital TDC based on a delay chain offers high throughput and a straightforward structure [9], making it a popular choice with diverse applications.…”

Section: Introductionmentioning

confidence: 99%

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

Li,

Gao

2024

Micromachines

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To reduce the power consumption of a TDC in high-speed applications, a TDC architecture applied to SS ADC is proposed to reduce redundant counting. This structure can remove the identical part between two rows of pixel signals in a CMOS image sensor by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. This structure requires the simultaneous readout of two rows of pixels in the high-speed CMOS image sensor. In the 110 nm CMOS process, simulation results show that the designed 5-bit TDC achieves an effective number of bits (ENOB) at 4.72 bits and a figure-of-merit (FOM) at 104.7–162.3 fJ/step, with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

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Section: Introductionmentioning

confidence: 99%

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

Li,

Gao

2024

Micromachines

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“…A time-to-digital converter (TDC) is a circuit that measures the time difference between two input events or pulse widths and is widely used in devices such as laser rangefinders, true random number generators, time-of-flight measurements, positron emission tomography scanners, and all digital phase-locked loops (AD PLL). There are many architectures for high resolution TDC, including a vernier based delay chain TDC[1], a time-amplifier based TDC [2,3], and a gated ring oscillator (GRO) TDC [4]. Pure digital TDC based on a delay chain has the advantages of high throughput and simple structure [5], therefore, it is increasingly appearing in various applications.…”

Section: Introductionmentioning

confidence: 99%

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

Li,

Gao

2024

Preprint

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To reduce the redundant counting of TDC in high-speed applications and thus reduce power consumption, a TDC architecture is proposed to quantify the difference between two adjacent rows of pixel signals. This structure can remove the identical part between two rows of pixel signals by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. In the 110nm CMOS process, simulation results show that this design achieves an effective number of bits (ENOB) of 4.72 bits and a Figure of Merit (FoM) of 104.7 fJ/step - 162.3 fJ/step with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

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“…However, some recent works demonstrated also remarkable results, especially those using heavily interleaved SAR ADCs. Two examples using with 64× are the work of Seual et al [7] and Liu et al [8] both presented in 2022. In [7], an extremely high sample rate of 112 GS/s was achieved, but the overall power consumption was quite high with 315.…”

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confidence: 99%

“…2 mW and 189.1 mW overall and for the ADC only, respectively. In [8], a very effective 10 GS/s ADC was presented providing a FoM W of 24.6 fJ/conv.step and a FoM S of 152.6 dB. Both of these works utilized an advanced 5 nm CMOS process, which offers very good conditions for high-speed digital design as well as area and power efficiency.…”

mentioning

confidence: 99%

“…Still, this is also an impressive work and it utilizes an older 40 nm technology and 128× TI. In our design, the sample rate per ADC core is higher compared to [8][12] and the power efficiency per ADC core is lower compared to [7][12] and we expect a sampling rate of 40 GS/s and 80 Gs/s with a power consumption of approximately 150 mW and 300 mW for future 64× and 128× TI, respectively.…”

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confidence: 99%

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A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

Matthus

Buhr

Ellinger

2023

Preprint

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This letter presents the design and measurement results of a 2.5 GS/s 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) with real-time data output via the JESD204B protocol using two lanes at 12.5 Gb/s each. The ADC is implemented in a 22-nm fully-depleted silicon-on-insulator (FDSOI) technology and consists of four time interleaved ADC cores. It consumes 43 mW overall, while the analog frontend including the four ADC cores and the interleaver consumes only 7.8 mW. In the first Nyquist zone, the effective number of bits (ENOB) is larger than 6.1 bit leading to a Walden Figure-of-Merit (FOM_W) of 45 fJ/conv.-step and a Schreier Figure-of-Merit (FOM_S) of 150.5 dB. Integral (INL) and differential nonlinearity (DNL) are both well below 0.5 LSB for all measurement scenarios.

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A 10GS/s 8b 25fJ/c-s 2850um² Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

Cited by 24 publications

References 5 publications

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

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A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

Cited by 24 publications

References 5 publications

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

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Product

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A 10GS/s 8b 25fJ/c-s 2850um² Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology