A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure

Sakashita, K.; Ueda, Mitsuru; Arakawa, T.; Asai, S.; Fujimura, Taku; Ohkura, I.

doi:10.1109/jssc.1985.1052322

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1986

1989

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Cited by 5 publications

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“…The number of logic circuits on CMOS gate array chips have increased with time [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Gate array chips have transistor assemblages on "lattice" positions.…”

Section: Historical Backgroundmentioning

confidence: 99%

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Osburn

Reisman

1987

J Supercomput

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This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

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