2008 9th International Conference on Solid-State and Integrated-Circuit Technology 2008
DOI: 10.1109/icsict.2008.4734970
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A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication

Bing Fan
1
,
Luo-sheng Li
2
,
Zi-qiao Chu
3
et al.
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