A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN

Siddiqui, M. Sultan M.; Sharma, Sudhir Kumar; Porwal, Saurabh; Pannalal, Khatik Bhagvan; Kumar, Sudhir

doi:10.1109/iscas.2019.8702335

“…However, this circuit utilizes a transmission gate for single-ended read/write operation, that leads to a reduction in write static noise margin (WSNM). Various read decoupled [33][34][35][36] and read buffers [28,30,31,[37][38][39][40][41][42][43][44][45] (see figure 5) based techniques have been used to to simultaneously RSNM and WSNM.…”

Section: Overview Of Pre-existing Sram Designsmentioning

confidence: 99%

“…The leakage power is reduced in this work on the cost of one extra transistor per bit-cell. Tae-Hyoung Kim et al [38,39] proposed further improvement to this circuit to realize similar stability parameters by cutting down more leakage power using an additional pull-up transistor. Compared to [37], this reduction in leakage is achieved at the cost of two additional transistors.…”

Section: Overview Of Pre-existing Sram Designsmentioning

confidence: 99%

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Sachdeva,

Sharma,

Bhargava

et al. 2024

Phys. Scr.

4

0

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Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read-and-hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21× and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99× compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

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“…2a. The read buffer consists Various read buffers (a)CONV8T [16] (b)CAL10T [17] (c) KIM10T [18] (d) NAV8T [19] (e) LIN9T [20] (f) MH9T [21] (g) YOU9T [22] (h) PAS9T [23] (i) WANG9T [4]; (j) ANISXY10T [24] (k) JIA8T [25] (l) MAR10T [26] (m) SHO10T-P1 [27] (n) SHO10T-P2 [27] (o) SHO10T-P3 [27] (p) SUL10T [28]. of two transistors R1 and R2, of which R1 is controlled by node QB of 6T cell and R2 is controlled by row based RWL signal.…”

Section: A Decoupled Read Path 1) Using Single-ended Sensingmentioning

confidence: 99%

“…Due to the data-independent leakage pattern, the RBL voltage for read '1' is always larger than that for read '0' with a high voltage swing. Sultan et al in [28] [30], [31] (b) SONG-D10T [32] (c) WU-Z8T [33] (d) LIU-D9T [34] (e) KUL-D8T [35] as shown in Fig. 2p .…”

Section: A Decoupled Read Path 1) Using Single-ended Sensingmentioning

confidence: 99%

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

3

0

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In order to meet the ultra-low power requirement of modern digital systems, voltage scaling is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides an extensive review of various designs and techniques for solving issues related to SRAM cell stability. Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement, most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current responsible for storing the data) or strengthening of access transistors (to enhance the write current). It includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost, VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL (NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of choice for various categories.

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“…FIGURE 2.Various read buffers (a)CONV8T[16] (b)CAL10T[17] (c) KIM10T[18] (d) NAV8T[19] (e) LIN9T[20] (f) MH9T[21] (g) YOU9T[22] (h) PAS9T[23] (i) WANG9T[4]; (j) ANISXY10T[24] (k) JIA8T[25] (l) MAR10T[26] (m) SHO10T-P1[27] (n) SHO10T-P2[27] (o) SHO10T-P3[27] (p) SUL10T[28].…”

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A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

2

0

View full text Add to dashboard Cite

In order to meet the ultra-low power requirement of modern digital systems, voltage scaling is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides an extensive review of various designs and techniques for solving issues related to SRAM cell stability. Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement, most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current responsible for storing the data) or strengthening of access transistors (to enhance the write current). It includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost, VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL (NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of choice for various categories.

show abstract

A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN

Cited by 7 publications

References 13 publications

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

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