A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

Hou, Bing; Chen, Hua; Wang, Zhiyu; Mo, Jianchu; Chen, Junli; Yu, F. Richard; Wang, Wenbo

doi:10.3390/s17020223

Cited by 3 publications

(4 citation statements)

References 16 publications

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“…Bluetooth is designed for the short distance communication with extremely low power consumption and simple communication protocol [5,6]. Therefore, Bluetooth is the standard communication idea for the sensor system [7][8][9][10]. Bluetooth Low Energy (BLE) plays an important role in achieving lower cost, lower power, and compact size.…”

Section: Introductionmentioning

confidence: 99%

“…One antenna is shared between the Tx and Rx for reducing the size of the system, as shown in Figure 1. The key component that realizes this system is the radio frequency (RF) switch called the Single Pole Double Throw (SPDT) switch [5][6][7][8][9]. The SPDT switch connects the transmit path or the receive path to the antenna in the Tx or Rx mode, respectively, while disconnecting the other path.…”

Section: Introductionmentioning

confidence: 99%

“…Bluetooth is the standard communication idea for the sensor system [7][8][9][10]. Bluetooth Low Energy (BLE) plays an important role in achieving lower cost, lower power, and compact size.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

et al. 2018

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In the IoT/wearable devices, the antenna is shared with the receiver and transmitter of the transceiver. This requires the control of the switch between the antenna and the control circuitry to achieve both low insertion loss and high isolation. This paper presents a low insertion loss and high isolation switch based on Single Pole Double Throw (SPDT) switch for 2.4 GHz Bluetooth low power (BLE) transceiver. The body-floating technique is used to improve the insertion loss’s performance. An ultra-small on-chip matching network with high Q-factor is proposed. The shunt transistors are used as active shunt capacitors that create the active matching network to improve isolation characteristics. The proposed SDPT switch was designed using 55 nm CMOS process with the total area of 110 μm × 210 μm. The insertion loss and isolation characteristics of the proposed SPDT switch observed at 2.4 GHz are 1.85 dB and 40 dB, respectively.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

et al. 2018

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“…Among the several functional blocks of a sensor node, most of the available power is used for carrier signal generation for data transmission. Using a local oscillator for carrier generation not only necessitates a significant amount of power consumption, but it is also quite difficult to achieve sufficient accuracy over processvoltage-temperature (PVT) variations [2]. Thus, it is challenging to implement a low-power wireless communication architecture in low-cost WSNs without the availability of a stable reference frequency.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

Naveed,

Dix

2023

JLPEA

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A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

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On Wireless Sensor Network Models: A Cross-Layer Systematic Review

Ojeda

Méndez

Fajardo

et al. 2023

JSAN

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Wireless sensor networks (WSNs) have been adopted in many fields of application, such as industrial, civil, smart cities, health, and the surveillance domain, to name a few. Fateway and sensor nodes conform to WSN, and each node integrates processor, communication, sensor, and power supply modules, sending and receiving information of a covered area across a propagation medium. Given the increasing complexity of a WSN system, and in an effort to understand, comprehend and analyze an entire WSN, different metrics are used to characterize the performance of the network. To reduce the complexity of the WSN architecture, different approaches and techniques are implemented to capture (model) the properties and behavior of particular aspects of the system. Based on these WSN models, many research works propose solutions to the problem of abstracting and exporting network functionalities and capabilities to the final user. Modeling an entire WSN is a difficult task for researchers since they must consider all of the constraints that affect network metrics, devices and system administration, holistically, and the models developed in different research works are currently focused only on a specific network layer (physical, link, or transport layer), making the estimation of the WSN behavior a very difficult task. In this context, we present a systematic and comprehensive review focused on identifying the existing WSN models, classified into three main areas (node, network, and system-level) and their corresponding challenges. This review summarizes and analyzes the available literature, which allows for the general understanding of WSN modeling in a holistic view, using a proposed taxonomy and consolidating the research trends and open challenges in the area.

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A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks

Cited by 3 publications

References 16 publications

40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

On Wireless Sensor Network Models: A Cross-Layer Systematic Review

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