A 11-mW quadrature frequency tripler with fundamental cancellation

Abstract

A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR 1 ) achieves more than 35dB, and the conversion gain achieves -4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4x1.1 mm 2 .