A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Bailey, James; Shakiba, Hossein; Nir, Ehud; Marderfeld, Grigory; Krotnev, Peter; LaCroix, Marc-Andre; Cassan, David; Tonietto, Davide

doi:10.1109/jssc.2021.3109167

Cited by 24 publications

(9 citation statements)

References 20 publications

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“…To show this, we can first assume that 𝑎 5 , 𝑎 7 = 0 for simplicity, and define ℎ 𝑒 = ℎ 𝑐ℎ ⨂h FFE , with ∑ ℎ 𝑒 (𝑖) = 𝑖 1. If ℎ 𝑒 (1) is the impulse response element corresponding to the main cursor, the value of 𝑣 𝑐𝑜𝑟𝑟 is also dependent on the residual ISI component (ℎ 𝑒 (1) − 1) that hides the nonlinearities:…”

Section: Calibration Loop Operationmentioning

confidence: 99%

“…This led to a rising interest in high-speed wireline communication systems with ever-increasing data rates, especially in data center applications. As of now, the most employed modulation in SerDes transceivers is Pulse Amplitude Modulation with four levels (PAM-4) [1][2][3], which allows doubling the data rate using the same symbol rate compared to Non-Return-to-Zero (NRZ) modulation. To achieve even higher data rates, the symbol rate of the system can be increased, but this approach is limited by the bandwidth of the channel.…”

Section: Introductionmentioning

confidence: 99%

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A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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Section: Calibration Loop Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Pasquo

Monaco²,

Ghittori³

et al. 2022

Electronics

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show abstract

“…Digital DFE implementations address this with parallelism, implying a complexity and power consumption that increases exponentially with the number of taps [12]. Recently, however, novel DFE architectures break this difficult tradeoff allowing for the pipelining of DFE logic [22]- [24].…”

Section: Decision Equalization (Dfe)mentioning

confidence: 99%

Optimal Optical Receivers in Nanoscale CMOS: A Tutorial

Radi

Abdelrahman

Liboiron-Ladouceur

et al. 2022

IEEE Trans. Circuits Syst. II

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The integration of optical receivers in nanoscale CMOS technologies is challenging due to less intrinsic gain and more noise compared to SiGe BiCMOS technologies. Recent research revealed that low-noise, high-gain, and lowpower CMOS optical receivers can be designed by limiting the bandwidth of the front-end followed by equalization techniques that benefit from good switching characteristics offered by CMOS technologies. In this tutorial brief, the operation of decision-feedback equalization, feed-forward equalization, and continuous-time linear equalization is reviewed in the context of high baud-rate 2-PAM and 4-PAM modulation. Recent advances and techniques in 4-PAM optical receivers are reviewed and compared in terms of speed, sensitivity, bandwidth, and efficiency.

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“…In [5], we demonstrated the effectiveness of DMT on a channel with a notch. However, the recent trend in most backplane and chip-to-chip channels is that they are quite smooth but can be lossy at high frequencies [13]- [16]. Previously, we presented simulation results on a DMT link operating over a smooth channel in [6].…”

Section: Introductionmentioning

confidence: 99%

Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading

et al. 2022

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This paper elucidates the relative benefits of bit loading and power loading for discrete multitone (DMT) modulation over wireline links. There is considerable variability in the use of bit and power loading in recent research on DMT for wireline applications. Here, we first compare different combinations of bit and power loading schemes in simulations. We propose a method for dynamically adjusting DMT bit and power profiles based on the bit error distribution across sub-channels, as determined by the receiver. We then present experimental results showing DMT operation at 75 Gb/s with a spectral efficiency of 2.5 b/sample over a channel with a smooth magnitude response exhibiting 26 dB attenuation at half the sampling rate and a loss of 33 dB at 1/4 the data rate (i.e., the Nyquist rate of a 4-level pulseamplitude modulated link at the same data rate). The proposed dynamic bit and power allocation method reduces the bit error rate from 3 × 10 −3 to 2 × 10 −5 , measured with 23,265,420 bits.INDEX TERMS Bit error rate (BER)-aware, bit loading, discrete multitone (DMT), orthogonal frequencydivision multiplexing (OFDM), power loading, wireline communication.

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A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

Cited by 24 publications

References 20 publications

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Optimal Optical Receivers in Nanoscale CMOS: A Tutorial

Spectrally Efficient DMT Operation With BER-Informed Dynamic Bit and Power Loading

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