A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Peng, Xiao; Chen, Zhixiang; Zhao, Xiongxin; Zhou, Dajiang; Goto, Satoshi

doi:10.1109/asscc.2011.6123576

Cited by 18 publications

(14 citation statements)

References 8 publications

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“…Binary input AWGN channel model is considered, with 20 decoding iterations. It can be seen that the simulation results corroborate the analytic results from Section III-A, in terms of SNR gain / loss provided by NS-FAIDs, as compared to MS. For comparison purposes, we have further included simulations results for the floatingpoint Belief Propagation (BP) decoder [12], as well as the MS decoder with (3,5) and (2, 4)-quantization.…”

Section: A Regular Ldpc Codesmentioning

confidence: 99%

“…In this context, Low-Density Parity-Check (LDPC) codes are recognized as the foremost solution, due to the intrinsic capacity of their decoders to accommodate various degrees of parallelism. They have found extensive applications in modern communication systems, due to their excellent decoding performance, high throughput capabilities [1]- [4], and power efficiency [5], [6], and have been adopted in several recent communication standards.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Nguyen-Ly

Savin

et al. 2018

IEEE Trans. VLSI Syst.

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Abstract-This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

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Section: A Regular Ldpc Codesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Nguyen-Ly

Savin

et al. 2018

IEEE Trans. VLSI Syst.

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“…The proposed decoder compares favorably with prior art by achieving both good hardware and energy efficiency. Only one work [13] (using SRAM macrocells) has slightly better hardware efficiency, at the cost of worse energy efficiency, while only one work [14] has slightly better energy efficiency, at the cost of worse area efficiency. Compared to [15], which is also based on SRAM macrocells, the proposed D-SCM based decoder implementation has both better hardware and better energy efficiency.…”

Section: B Comparison With Prior-art Implementationsmentioning

confidence: 99%

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Meinerzhagen

Bonetti

Karakonstantis

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refreshfree D-SCMs was implemented in a 90 nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

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“…An MSCS block occupies just tens of thousands of gates, but a highly parallel QC-LDPC decoder usually includes around a dozen MSCS blocks [4], [5]. The area of an MSCS block, therefore, affects the total area of a decoder significantly, making area reduction a main subject of research on MSCS structures.…”

Section: Introductionmentioning

confidence: 99%

“…Another kind of MSCS structure is based on normal barrel rotators. To support various sizes, two barrel rotators are placed in parallel [4], [6] or series [7]. The other kind is based on a Benes network, which can route any N × N permutation [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Kang

Yang

2017

ETRI Journal

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The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a lowcomplexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

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A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Cited by 18 publications

References 8 publications

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

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