A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Ishibashi, Koji; Komiyaji, K.; Morita, S.; Aoto, T.; Ikeda, Shuji; Asayama, K.; Koike, A.; Yamanaka, Toshiaki; Hashimoto, Norikazu; Iida, Hiroyasu; Kojima, Fumio; Motohashi, K.; Sasaki, K.

doi:10.1109/4.280689

Cited by 20 publications

(2 citation statements)

References 9 publications

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“…We should notice that with the use of offset-compensating techniques or/and careful centroid layout [50] used for SRAM memories, the offset voltage can be significantly reduced (4mV value was reported in [50]). However, taking into account the huge number of sense amplifiers in register files, and area and/or power penalties of these techniques, we assume that they will not be used for register files in the nearest future.…”

Section: Differential Sensing Schemementioning

confidence: 98%

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

114

121

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Victor V. Zyuban When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as 'sleep modes', at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next-generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microar-CHAPTER 6: IMPLEMENTATION OF THE ENERGY-EFFICIENT MULTI-CLUSTER ARCHITECTURE .

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Section: Differential Sensing Schemementioning

confidence: 98%

Inherently lower-power high-performance superscalar architectures

Zyuban

Kogge

2001

IEEE Trans. Comput.

114

121

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“…The scheme reduces the total current to 102 fA. To cope with the increased SER caused by the reduced signal charge in the standby mode, an ECC was incorporated with a speed penalty of 3.2 ns and an area penalty of 9.7%, although an additional cell-capacitor can also improve the SER [ Figure 5(a)] [45,46]. Figure 11 shows another solution.…”

Section: Sram Cellsmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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A size-configurable two-port SRAM macrocell with power reduction architecture using a writing-enable signal

Shibata

Katoh

1999

Electron. Comm. Jpn. Pt. II

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A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Cited by 20 publications

References 9 publications

Inherently lower-power high-performance superscalar architectures

Inherently lower-power high-performance superscalar architectures

Review and future prospects of low-voltage RAM circuits

A size-configurable two-port SRAM macrocell with power reduction architecture using a writing-enable signal

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