A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Harwood, M. G.; Warke, N.; Simpson, R.; Leslie, T.C.; Amerasekera, A.; Batty, Sean; Colman, D.; Carr, Edward Ellis; Venugopal, Gunasekaran; Hubbins, S.; Hunt, P.C.; Joy, A.K.; Khandelwal, Pulkit; Killips, B.; Krause, Thomas W.; Lytollis, S.; Pickering, Andrew; Saxton, M.; Sebastio, D.; Swanson, G.; Szczepanek, Andre; Ward, T.G.; Williams, Jean; Williams, R.; Willwerth, T.

doi:10.1109/isscc.2007.373481

Cited by 98 publications

(40 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…This simple frontend circuitry is use to perform prefiltering. A Continuous-Time Linear Equalizer (CTLE) a very common building block for receiver pre-filtering, in a mixed mode receiver [5]. Figure 1 shows a general ADC-based receiver architecture which comprises of a HPF/FIR filter whose input in turn is fed to digital equalizer/sequence detector.…”

Section: Analog and Mixed-mode Frontendmentioning

confidence: 99%

Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver

Aherrao¹,

Varade²

2013

IJCA

View full text Add to dashboard Cite

This paper presents design & Simulation of High Speed, Low Powered ADC for Serial link Receiver. This ADC based receiver uses a low gain analog and mixed mode pre-equalizer in conjunction with the non-uniform reference levels for ADC. This combination compensates for both front-end nonideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. This receiver is based on a low power design of Analog to Digital converter, thus lowering the power consumption of overall system. Tanner tool 13.0 is used for the simulation of the proposed design. From the simulation results it has been observed that the modules used in the proposed ADC lowers the power consumption.

show abstract

Section: Analog and Mixed-mode Frontendmentioning

confidence: 99%

Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver

Aherrao¹,

Varade²

2013

IJCA

View full text Add to dashboard Cite

show abstract

“…As the ever-growing demands for higher data rate call for more sophisticated equalization schemes and the advances in fabrication technology favor digital circuit implementation, backplane receivers that rely on a frontend analog-to-digital converter (ADC) and a digital equalizer are gaining more popularity in these years [1][2][3][4][5][6][7][8]. Such ADC-based receivers not only provide opportunity to utilize advanced digital signal processing (DSP) techniques to perform higher-level of equalization, but also enable more robust circuit implementation against process variation, leakage, and noise.…”

Section: Introductionmentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

show abstract

“…2(a), a digital phase detector compares the phase of the incoming data with the phase of the sampling clock. A low pass filter then sends digital control bits to a digitally-controlled oscillator (DCO) or a phase-interpolator (PI) in order to adjust the phase of the sampling clock [2]. In this system, there is a feedback loop containing both digital and analog components and, as a result, the delay of the feedback loop plays an important role in the stability of the system [3].…”

Section: Introductionmentioning

confidence: 99%

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

Abiri

Sheikholeslami

Tamura

et al. 2011

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-This paper proposes an adaptation engine for a 2 blind sampling ADC-based receiver. The proposed adaptive engine uses a triangular desired waveform, instead of two fixed desired levels, to shape the equalizer output in spite of blind nature of sampling. The measured results confirm the adaptive engine restores a 5 Gb/s eye subjected to 13 dB of attenuation at Nyquist frequency to an equivalent of 320 mV of vertical opening. The receiver consumes 192 mW, out of which 78 mW is used by the digital CDR.

show abstract

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Cited by 98 publications

References 3 publications

Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver

Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver

ADC-Based Backplane Receivers: Motivations, Issues and Future

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

Contact Info

Product

Resources

About