A 12 b 200 kS/s 0.52 mA 0.47 mm2 Algorithmic A/D Converter for MEMS Applications

Abstract

This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm 2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm 2 and consumes 0.94 mW at 200 kS/s and 0.

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

“…Conventional ADCs employ external 0.1 F bypass capacitors and/or internal RC-filters at the reference voltage outputs to solve this problem [12,15]. However, the proposed reference circuits reduce the noise without any internal and external bypass capacitors [16]. Considering the required signal-settling behavior of the top and bottom reference voltages, GND+0.25 V and GND−0.25 V, for a 1.0 V p-p signal swing, the reference voltages need to settle down within 10 ns, which is 50% of a half clock cycle at 25 MHz.…”