A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters

Tseng, Wei-Hsin; Lee, Wei‐Liang; Huang, Changyang; Chiu, Pao-Cheng

doi:10.1109/asscc.2015.7387506

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…Such a large capacitance would result in a large chip area and a high power consumption to drive it. To overcome the design penalty, a differential DAC digital foreground calibration based on [18] is designed in this SAR ADC.…”

Section: Dac Foreground Calibrationmentioning

confidence: 99%

“…However, the implementation of this calibration requires an additional block circuit and a large area. A foreground digital calibration is proposed in [18,19], which considers low-bit capacitances as the ideal ones and uses them to estimate the weight of high-bit capacitances. However, the weight estimation errors of LSB capacitances will propagate exponentially to those of MSB ones.…”

Section: Introductionmentioning

confidence: 99%

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A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

He,

Qiao,

Xing

et al. 2024

JLPEA

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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

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Section: Dac Foreground Calibrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

He,

Qiao,

Xing

et al. 2024

JLPEA

View full text Add to dashboard Cite

show abstract

“…Furthermore, to achieve the high resolution in SAR-ADC, a capacitor mismatching calibration is required. For this, the digital background technique was implemented in Tseng et al (2015). Moreover, to remove the overhead of the hardware, a multiplexer was planted.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, to remove the overhead of the hardware, a multiplexer was planted. It connects itself with the reference voltage and ground (Tseng et al, 2015).…”

Section: Introductionmentioning

confidence: 99%

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Faheem

Zhong

Wang

et al. 2021

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Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

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An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration

Chen

Ren

2018

Microelectronics Journal

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A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters

Cited by 9 publications

References 4 publications

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration

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A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters

Cited by 9 publications

References 4 publications

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration

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An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration