A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

Zeloufi, M.

doi:10.1088/1748-0221/11/01/c01030

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…The large number of readout channels demands low power consumption to release the pressure of the cooling system on high altitude mountains. Therefore, the SAR architecture [21][22] is adopted for its simplicity and power efficiency in deepsub-micron CMOS technology compared with pipelined architecture [8,23]. The rest of this paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

Liu

Qin

et al. 2016

Chinese Phys. C

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High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on power-efficient Successive Approximation Register (SAR) architecture, which incorporates the key parts such as Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and asynchronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.

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Section: Introductionmentioning

confidence: 99%

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

Liu

Qin

et al. 2016

Chinese Phys. C

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A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

Zhang

Qiu

Shan

et al. 2020

IEICE Electron. Express

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In this paper, a 16-bit 8-MS/s successive approximation register analog-to-digital converter (SAR ADC) with a foreground calibration technique is proposed. A nonbinary searching algorithm is adopted to speed up the conversion rate and overcome the incomplete settling of the reference voltage. A foreground calibration method with low-cost circuitry is implemented to detect the mismatch of the capacitor digital-to-analog converter in calibration mode and compensate for the output code in conversion mode. The simulation results show that the peak signal-to-noise and distortion (SNDR) and spurious free dynamic range (SFDR) are improved from 69.98 dB to 91.39 dB and 73.94 dB to 99.41 dB, respectively. Moreover, the proposed ADC uses a hybrid-charge-supply power structure. The sampling circuit operates at 3.3 V to maintain a wide dynamic range, the logic circuit operates at 1.2 V to decrease the conversion time and power consumption, and the total power consumption is 45 mW at 8 MS/s.

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A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration

Zhang

Shan

Dong

2020

IEICE Electron. Express

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A 12 bit 40 MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LAr calorimeter readout

Cited by 3 publications

References 8 publications

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure

A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration

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