A 12-bit intrinsic accuracy high-speed CMOS DAC

Bastos, J.; Marques, A.; Steyaert, Michiel; Sansen, Willy

doi:10.1109/4.735536

Cited by 284 publications

(142 citation statements)

References 17 publications

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“…1(a) shows a representative structure of a 2-D current-matrix-based current-steering DAC with a schematic of a 1-bit cell. The structure is good for cell matching owing to the compact current source array, often with common centroid or randomized cell placement [3][4][5]. However, one drawback with this Manuscript received Oct. 6, 2011; revised Jan. 29, 2012.…”

Section: Design Considerations Formentioning

confidence: 99%

“…In order to alleviate the effect of C 0 at high frequency, many designs have employed cascode current sources (M CAS + M CS ) [2,3] to increase both the static and dynamic output impedance. The cascode transistor (M CAS ) on top of the current source (M CS ) provides high output resistance at low frequency.…”

Section: Design Considerations Formentioning

confidence: 99%

“…One of the critical design issues with high speed DACs is how to preserve the dynamic linearity (spurious free dynamic range, SFDR) at high frequency signals while avoiding reduction of the output impedance [1,2]. The common-centroid based twodimensional (2-D) current source array [2,3] is a suitable DAC architecture for good static linearity (DNL/INL). However, when it comes to the dynamic linearity, i.e.…”

Section: Introductionmentioning

confidence: 99%

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A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

Kim¹,

Kim²,

Lee³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only 0.0546 mm 2 (0.21 mm x 0.26 mm).

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Section: Design Considerations Formentioning

confidence: 99%

Section: Design Considerations Formentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

Kim¹,

Kim²,

Lee³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…In this case, the INL error for an -bit DAC is due to the combination of LSB current sources (independently of the DAC segmentation 1 ). The LSB current source minimum relative accuracy required to achieve a certain INL upper bound with a given statistical yield, as a function of the DAC resolution, is [10], [13] ( 3) where is the inverse cumulative normal distribution, and is the percentage of manufactured DACs with an INL smaller or equal than the upper bound .…”

Section: A Current Source Accuracymentioning

confidence: 99%

Mismatch and Dynamic Modeling of Current Sources in Current-Steering CMOS D/A Converters: An Extended Design Procedure

Albiol

González

Alarcón

2004

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents an improved modeling of the effect of random mismatch and current source transient switching behavior on the performance of current-steering CMOS digital-toanalog converters (DACs). The work considers two current source cell topologies, namely a simple cell and a cascoded cell, obtaining the relation of transistors design parameters to the static and dynamic models. On the one hand, a mismatching statistical analysis is applied to all the transistors of the current source circuit, which allows to define design expressions relating the circuit parameters to the DAC specifications without the need of arbitrary design margins or Monte Carlo simulations. On the other hand, improved analysis of the current source switching characteristics provides a more realistic modeling of the relation between transistors sizes and output current settling time. By including these two improved models into the usual design procedure, circuit sizing for optimum settling time and proper static behavior can be obtained analytically, reverting in smaller current source area, and, hence, in an overall DAC area reduction.

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“…Current-steering digital-to-analog converters (DACs) have been widely used in high-speed DACs requiring a large spurious free dynamic range (SFDR) and a wide bandwidth [1]- [9]. The current-steering DACs are based on a segmented structure using unary-encoded and binary-weighted currentsource cells, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%