A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS

Huang, Sheng; Liu, Shubin; Hu, Jin; Wang, Riyan; Zhu, Zhangming

doi:10.1109/lmwc.2019.2909656

Cited by 12 publications

(6 citation statements)

References 6 publications

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“…Compared to other PLL works, the proposed CPPLL can achieve a better phase noise. Yan D L 2012 12 Parkalian N 2018 13 Huang S 2019 14 Li H 2019 15 This study…”

Section: Measurement Resultsmentioning

confidence: 90%

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Zhou

Kang

et al. 2022

Micro & Optical Tech Letters

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A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption.

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“…Compared to other PLL works, the proposed CPPLL can achieve a better phase noise. Yan D L 2012 12 Parkalian N 2018 13 Huang S 2019 14 Li H 2019 15 This study…”

Section: Measurement Resultsmentioning

confidence: 90%

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

Zhou

Kang

et al. 2022

Micro & Optical Tech Letters

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“…There are three kinds of PLL architectures 3 : PLL using a fundamental voltage-controlled oscillator (VCO), PLL using an N-push VCO, and PLL followed by a frequency multiplier. For the first one, [4][5][6][7] its frequency range depends on the tuning range of the VCO. In Ref.…”

Section: Introductionmentioning

confidence: 99%

“…In Ref. [7], a class-C cross-coupled VCO with an amplitudeadjustment circuit is adopted to increase current during the startup process and stabilize the VCO amplitude. It achieves a competitive phase noise of À106 dBc/Hz at 1-MHz offset from a 11.96 GHz carrier, but the locking range is limited by the single-core fundamental topology, which is only 16.2%.…”

Section: Introductionmentioning

confidence: 99%

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

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“…A phase-locked loop (PLL) is an important building block in communication systems such as Wireless Local Area Network (WLAN) [1,2,3,4,5]. Voltage-Control Oscillator (VCO) is a critical module of PLL, and its performance directly influences the performance of PLL [6,7,8,9].…”

Section: Introductionmentioning

confidence: 99%

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

Tian

Huang

et al. 2021

IEICE Electron. Express

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In this paper, a 5.67-8.75 GHz LC VCO with small gain variation and reconfigurable buffer for 2.4 GHz-band WLAN applications is presented and implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The VCO gain is a strong function of the capacitance. For wide frequency tuning range meaning the large gain variation. The gain calibration scheme is proposed to obtain small gain variation across the frequency range. This letter proposes a reconfigurable buffer with adjustable amplitude, low jitter, and small supply coupling issues. The results show the proposed gain calibration scheme is very effective. The measured phase noise at 6.69 MHz offset is -123.2 dBc/Hz at 4.9 GHz output frequency.

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A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS

Cited by 12 publications

References 6 publications

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

A 5.67-8.75GHz LC VCO with small gain variation for 2.4GHz-band WLAN applications

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