A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration

El-Chammas, Manar; Murmann, Boris

doi:10.1109/vlsic.2010.5560315

Cited by 67 publications

(62 citation statements)

References 2 publications

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“…The SAR-type front-end ADCs take advantage of the low power consumption of a single SAR ADC. Since a SAR ADC consumes extremely low power, large number of ADCs (e.g., [8][9][10][11][12][13][14][15][16] can be timeinterleaved to achieve high aggregate sampling rate. To minimize the impact of phase mismatch between the sampling clocks and maximize the input bandwidth a master-slave T&H structure can be employed.…”

Section: Discussionmentioning

confidence: 99%

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ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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Section: Discussionmentioning

confidence: 99%

“…Meanwhile, to meet the tight power budgets of the backplane link system, power consumption of the front-end ADC should be minimized. Unfortunately, designing a high-speed ADC consuming low power is non-trivial [7,[9][10][11][12][13][14][15][16][17]. Flash ADCs are widely used for high-speed operation as they have short conversion times.…”

Section: Introductionmentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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“…Time-interleaved ADCs have previously been considered impractical because the solution for this issue is much more complicated than the PN injection for gain and offset errors. Recently, several solutions have been proposed [34][35][36], and the timeinterleaved architecture has become popular for high-speed A/D conversion. One of these solutions is based on digital correlation between the two interleaved channels [36].…”

Section: ) Detection Of Sampling Instant Mismatch By Correlationmentioning

confidence: 99%

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Shu

Ho²,

Chen

et al. 2016

SIP

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“…Analog-to-digital converters supporting very high sampling rates often use time-interleaving of multiple ADCs to reduce the requirements on the individual ADCs [40]. In an M -channel TI-ADC, the continuous-time signal x a (t) is sampled using M parallel ADCs as shown in Fig.…”

Section: Time-interleaved Adcsmentioning

confidence: 99%

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Pillai¹

2015

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An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TI-ADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs.iii Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor.Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lowe...

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A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration

Cited by 67 publications

References 2 publications

ADC-Based Backplane Receivers: Motivations, Issues and Future

ADC-Based Backplane Receivers: Motivations, Issues and Future

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Signal Reconstruction Algorithms for Time-Interleaved ADCs

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