A 1200-V GaN/SiC cascode device with E-mode p-GaN gate HEMT and D-mode SiC junction field-effect transistor

Wang, Yuru; Lyu, Gang; Wei, Jin; Zheng, Zheyang; Lei, Jiacheng; Song, Wenlei; Zhang, Long; Hua, Mengyuan; Chen, Kevin J.

doi:10.7567/1882-0786/ab4741

Cited by 10 publications

(2 citation statements)

References 23 publications

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“…When the device temperature increases, the carriers in the channel interact with the lattice vibrations and the carrier mobility (μ0) will reduce. The μ0 versus temperature is shown in (11).…”

Section: A Reasons For Changes In Static Characteristicsmentioning

confidence: 99%

“…However, its normally-on operation is highly undesirable from a practical operating point of view. Normally-on SiC JFET remains conductive when gate signal wasn't imposed, this can lead to the circuit losing effective control when DC bus voltage suddenly arrives, which is obviously unexpected for circuit designer [10], [11]. To solve this problem, the Si/SiC Cascode configuration has been proposed.…”

Section: Introductionmentioning

confidence: 99%

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Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Zhang,

Liu,

Zhou

2024

IEEE Open J. Power Electron.

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The Si/SiC Cascode device has been widely accepted in various applications, however, its reliability issue still remains a major concern and needs to be extensively investigated. In this paper, the degradation of a 750 V Si/SiC Cascode device under repetitive short-circuit (SC) tests is investigated at 400 V DC-link voltage. Static and dynamic characteristics are measured before and after the repetitive SC cycles. As the SC cycle increases, the degradation of the device becomes gradually significant. By linking changes in electrical properties to metallization degradation, the physical mechanism of device degradation has been uncovered in depth. Experimental results show that the continuous stress under repetitive SC cycle leads to an increase in the on-state resistance of Si/SiC Cascode device. Finite-element-model (FEM) simulations show that due to the pad current crowding in the source region, the source Al metallization temperature of the SiC JFET rapidly increases to the melting point and undergoes reconstruction, resulting in a significant increase in the source Al metallization resistance. In addition, it is found by scanning electron microscopy (SEM) that the gate metal aluminum of SiC JFET chip also undergoes reconstruction, which is the reason for the degradation of the dynamic characteristics. The research in this paper will provide useful evidences for device manufactures to design Si/SiC Cascode device with high reliability.

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Section: A Reasons For Changes In Static Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Zhang,

Liu,

Zhou

2024

IEEE Open J. Power Electron.

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Correlating Structural and Electrical Characteristics of Threading Dislocations in GaN -on- Si Heterostructures and p - n Diodes by Multiple Microscopy Techniques

et al. 2023

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Structural and electrical properties of aand a+c-type threading dislocations in metal organic vapor phase epitaxy grown Si-doped GaN (0001) were determined by combining multiple scanning probe microscopy approaches. The analysis examines the space charge region (SCR) formed around dislocation cores and clarifies the role it plays in influencing the local recombination, the surface potential characteristic and even the conductivity. The direct evidence of the SCR was obtained from a differential capacitance (dC/dV) measurement at dislocation sites on the (0001) surface. Experimental dC/dV(V) measurement results supported by Technology Computer-Aided Design calculations of capacitance accounting for the theoretical deep levels related to different atom core-structures of the identified dislocations revealed quantitative differences in their respective trap densities. This study was extended to p-n GaN vertical diodes to analyze doping distribution across the active layers. Through a correlated cross-sectional investigation combining electron channeling contrast imaging microscopy, the underlying dislocations within the depth limited by the screening of their SCRs were found to severely impact the homogeneity of the cross-sectional dC/dV contrast in the low-doped n-type drift layer of the diodes. This raises serious concern regarding any quantification effort by differential capacitance measurements in GaN-on-Si, where the dislocation density is in the order of 10 9 cm -2 .

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Dv/Dt-control of 1200-V Co-packaged SiC- JFET/GaN-HEMT Cascode Device

Lyu

Wang

Wei

et al. 2020

2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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A 1200-V GaN/SiC cascode device with E-mode p-GaN gate HEMT and D-mode SiC junction field-effect transistor

Cited by 10 publications

References 23 publications

Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Investigation on the Degradation Mechanism of Si/SiC Cascode Device Under Repetitive Short-Circuit Tests

Correlating Structural and Electrical Characteristics of Threading Dislocations in GaN -on- Si Heterostructures and p - n Diodes by Multiple Microscopy Techniques

Dv/Dt-control of 1200-V Co-packaged SiC- JFET/GaN-HEMT Cascode Device

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