A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang, Huajun; Berkhout, Marco; Makinwa, Kofi A. A.; Fan, Qinwen

doi:10.1109/isscc42614.2022.9731737

Cited by 2 publications

(6 citation statements)

References 3 publications

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“…To avoid the thermal and/or 1/f noise of current-steering or resistive DACs, a CDAC can be used to drive a closed-loop CDA based on the capacitively-coupled chopper-amplifier (CCCA) topology presented in [4]. Potential intermodulation between the DAC output waveform, which contains DAC images around multiples of f S as well as shaped quantization noise, and the various chopping and PWM tones must then be carefully mitigated.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

“…A 24-bit digital input is up-sampled to f S =768kHz (16×48kHz), reduced to 8 bits by a 6 th -order digital ΔΣ modulator (DSM1), and then converted into the analog domain by a CDAC. The latter drives a closed-loop CDA with an embedded CCCA front-end, a 14.4V 3-level PWM-based output stage, and feedback after the LC filter, enabling low noise and suppressing LC filter nonlinearity [4]. To compensate for the LC filter's phase shift, the loop filter must implement at least one zero, which inevitably causes some overshoot in its response to DAC transitions.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

“…The loop filter output is re-modulated by a 3-level analog PWM modulator switching at f PWM =4.992MHz, which is an odd (13 th ) harmonic of f CHOP . This avoids intermodulation distortion between the chopping and PWM sidebands [4]. However, this also means that f PWM (=6.5f S ) is not located at a multiple of f S, so some quantization noise folding will occur.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

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3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digitalinput CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak THD+N of about −98dB [2,3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, ISI, and intermodulation distortion. A prototype implemented in a 0.18μm BCD process achieves 120.9dB DR and −111.2dB peak THD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Ω/4Ω load with a 90%/86% efficiency.

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Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

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3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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“…2 There was a typo in the callout for R dc in Fig. 2 of the conference paper [21], which had the resistor in the middle of two nMOS switches. This is corrected in Fig.…”

Section: A Capacitively Coupled Chopper Preamplifiermentioning

confidence: 99%

“…This work presents a capacitively coupled chopper CDA that achieves 121.4-dB DR [21]. Unlike conventional chopper amplifiers, which process small input and output signals [18], [19] or are used in discrete-time switched-capacitor circuits [20], the proposed audio amplifier must process large continuous-time signals at both its low-voltage (LV) input (±1.8 V) and HV output (±14.4 V).…”

mentioning

confidence: 99%

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a class-D amplifier (CDA) with high dynamic range (DR). To eliminate the typically dominant noise contribution of a resistive feedback network, the input and feedback signals are chopped and applied to a capacitive feedback network. However, this leads to high-voltage (HV) transients at the input of the loop filter, which, due to timing and impedance mismatch in the chopped feedback network, could degrade linearity and even overstress low-voltage (LV) core devices. Robust processing of the HV chopped feedback signal is guaranteed with chopper timing skew correction, chopper impedance matching, and deadbanding. The prototype, implemented in a 180-nm bipolar-CMOS-DMOS (BCD) process, achieves 121.4 dB of DR, 5.9 dB higher than state-of-the-art closed-loop CDAs, and 8-μV RMS output-referred noise (A-weighted). It also achieves a peak total harmonic distortion (THD) + N of −109.8 dB and a peak efficiency of 93%/88% while driving 15 W/26 W into an 8-/4-load.

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A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio Amplifier

Cited by 2 publications

References 3 publications

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier

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