A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

Neda, Shilan; Yosefi, Ghader; Eskandarian, Abdollah

doi:10.1007/s10470-021-01822-1

Cited by 1 publication

(1 citation statement)

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“…IVIDE-by-eight frequency dividers (FDs) are used in sliding-IF receivers [1], [2] and phase-locked loops as shown in Fig. 1 [3], [4]. Normally they can be designed with three ÷2 current mode logic (CML) flip-flop-based frequency dividers (FDs) [5], [6], [7] or three ÷2 LC-tank injection-locked frequency dividers (ILFDs).…”

Section: Introductionmentioning

confidence: 99%

Current Reused 8:1 Injection Locked Frequency Divider Using Unbalanced Ring Oscillator Frequency Divider

Jang¹,

Hsieh²,

Yang³

et al. 2021

IEEE Access

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This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of 0.8044×0.72 mm 2 . The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

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