A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA

Abstract

Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device.Index Terms-Bin realignment, Field programmable gate array (FPGA), measurement throughput, multi-channel time-to-digital converter (TDC), RMS resolution, thermometer-to-binary encoder, time-to-digital converter.

A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA

“…A resource-efficient TDC design is especially desirable in these cases. Because the low temperature-dependency in 28 nm Xilinx FPGA has been found in our previous work [3], the calibration table on-line updating may not be needed if such FPGAs are used. This paper is presenting a method, hereafter called nonlinearity minimization-oriented (NMO) design method, to trade-off the TDC bin sizes and their uniformity, so that a reasonably high time resolution can be achieved without the aid of bin-by-bin calibration.…”

“…3(c) respectively, which requires a bin-by-bin calibration to correct for achieving a high time resolution. The calibration is normally fulfilled by a look-up table in an embedded block RAM and corresponding logic [3], which is a considerable resource consumption, especially for a multi-channel TDC system. Since there are a large number of zero-width bins in the original taps, the thermometer-to-binary encoder, which is recognized as the most resource-intensive part in a TDC [3], is unnecessarily complicated although the zero-width bins have no contribution for the final time resolution.…”

“…The calibration is normally fulfilled by a look-up table in an embedded block RAM and corresponding logic [3], which is a considerable resource consumption, especially for a multi-channel TDC system. Since there are a large number of zero-width bins in the original taps, the thermometer-to-binary encoder, which is recognized as the most resource-intensive part in a TDC [3], is unnecessarily complicated although the zero-width bins have no contribution for the final time resolution. If they are simply discarded, the number of effective bins is reduced and the actual average bin width is nearly twice the expected value, which increases the DNL and limits the final time resolution.…”

“…In recent years, techniques to implement time-to-digital converters (TDC) in FPGA has been widely investigated and advanced significantly [1]- [3]. Currently available root-mean-square (RMS) time measurement resolution less than 10 ps on FPGA has made the technique very attractive to many applications, such as time-of-flight positron emission tomography (TOF-PET) and particle physics experiments.…”

“…E. Bayer et al used the two methods to implement a multi-channel TDC on Virtex-4 Xilinx FPGA achieving the RMS resolution of 10 ps [8] and 5 ps [9] respectively. The latest work [3] used the method to implement a 128-channel, 710M samples/second and less than 10 ps RMS resolution TDC on a Kintex-7 device.…”