A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC

Jia, Tianyu; Mantovani, Paolo; Santos, Maico Cassel dos; Giri, Davide; Zuckerman, Joseph D.; Loscalzo, Erik Jens; Cochet, Martin; Swaminathan, Karthik; Tombesi, Gabriele; Zhang, Jeff; Chandramoorthy, Nandhini; Wellman, John-David; Tien, Kevin; Carloni, Luca P.; Shepard, Kenneth L.; Brooks, David; Wei, Gu-Yeon; Bose, Pradip

doi:10.1109/esscirc55480.2022.9911456

Cited by 12 publications

(6 citation statements)

References 10 publications

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“…Embedded computers integrate high-end SoCs with application-class cores, supporting virtualization and various privilege levels (and hence full-fledged OSs), embedded GPUs, and GBytes of high-performance off-chip LPDDR/DDR4/5 memories, connected through expensive, large and powerhungry mixed-signal DDR controllers, all within a power envelope of few watts [29], [31]- [33].…”

Section: A Socs For Standard and Micro-sized Uavsmentioning

confidence: 99%

“…To have a thorough comparison, we extend it also with SoC not explicitly optimized for UAVs but with similar general-purpose software performance and functionalities that could fit the purpose, namely Cheshire [34], the work from Jia et.al. [31], the STM32-H7 [5] and the work by Ju et.al. [11].…”

Section: Comparison With State-of-the-artmentioning

confidence: 99%

“…al. [11] consists of a homogeneous systolic array of RV32 cores, while Jia et al [31] instantiates a cluster of four RV64 cores along with a set of hardwired ASIC accelerators. More advanced nano-UAV SoCs, such as GAP9 [7] and Kraken [8], incorporate an RV32 CPU that can offload compute-intensive tasks to a parallel cluster of cores with the same ISA.…”

Section: Comparison With State-of-the-artmentioning

confidence: 99%

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Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Valente,

Veeran,

Sinigaglia

et al. 2023

2023 IEEE Hot Chips 35 Symposium (HCS)

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The rapid advancement of energy-efficient parallel ultra-low-power (ULP) µcontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next generation of unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant power and payload constraints while requiring advanced computing capabilities akin to standard drones, including real-time Machine Learning (ML) performance and the safe co-existence of general-purpose and real-time OSs. Although some advanced parallel ULP MCUs offer the necessary ML computing capabilities within the prescribed power limits, they rely on small main memories (<1MB) and µcontroller-class CPUs with no virtualization or security features, and hence only support simple bare-metal runtimes. In this work, we present Shaheen, a 9mm 2 200mW SoC implemented in 22nm FDX technology. Differently from state-of-the-art MCUs, Shaheen integrates a Linux-capable RV64 core, compliant with the v1.0 ratified Hypervisor extension and equipped with timing channel protection, along with a low-cost and low-power memory controller exposing up to 512MB of off-chip low-cost low-power HyperRAM directly to the CPU. At the same time, it integrates a fully programmable energy-and area-efficient multi-core cluster of RV32 cores optimized for general-purpose DSP as well as reduced-and mixed-precision ML. To the best of the authors' knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA. We demonstrate the capabilities of the proposed SoC on a wide range of benchmarks relevant to nano-UAV applications including general-purpose DSP as well as inference and online learning of quantized DNNs. The cluster can deliver up to 90GOp/s and up to 1.8TOp/s/W on 2-bit integer kernels and up to 7.9GFLOp/s and up to 150GFLOp/s/W on 16-bit FP kernels.

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Section: A Socs For Standard and Micro-sized Uavsmentioning

confidence: 99%

Section: Comparison With State-of-the-artmentioning

confidence: 99%

Section: Comparison With State-of-the-artmentioning

confidence: 99%

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Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Valente,

Veeran,

Sinigaglia

et al. 2023

2023 IEEE Hot Chips 35 Symposium (HCS)

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“…Unfortunately, AXI-Lite does not support bursts needed by high-performance systems. The ESP framework [4], [10] also provides an open-source implementation of its multi-plane NoC, supporting coherent and non-coherent endpoints. The NoC is a 2D mesh topology and uses a custom packet-based protocol.…”

Section: Related Workmentioning

confidence: 99%

PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge

Jain,

Cavalcante,

Bruschi

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packet-based protocols suffering from significant protocol translation overheads towards the endpoints. This paper proposes PATRONoC, an open-source fully AXI-compliant NoC fabric to better address the specific needs of multi-core DNN computing platforms. Evaluation of PATRONoC in a 2D-mesh topology shows 34 % higher area efficiency compared to a state-of-the-art classical NoC at 1 GHz. PATRONoC's throughput outperforms a baseline NoC by 2-8× on uniform random traffic and provides a high aggregated throughput of up to 350 GiB/s on synthetic and DNN workload traffic.

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“…2) to evaluate processing performance and energy. Along with voltage, we also scale the frequency based on measured results on a deep-learning accelerator reported in [30].…”

Section: A Experimental Setupmentioning

confidence: 99%

Analyzing and Improving Resilience and Robustness of Autonomous Systems

Wan

Swaminathan²,

Chen³

et al. 2022

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

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Autonomous systems, such as Unmanned Aerial Vehicles (UAVs), are expected to run complex reinforcement learning (RL) models to execute fully autonomous positionnavigation-time tasks within stringent onboard weight and power constraints. We observe that reducing onboard operating voltage can benefit the energy efficiency of both the computation and flight mission, however, it can also result in on-chip bit failures that are detrimental to mission safety and performance. To this end, we propose BERRY, a robust learning framework to improve bit error robustness and energy efficiency for RL-enabled autonomous systems. BERRY supports robust learning, both offline and on-board the UAV, and for the first time, demonstrates the practicality of robust low-voltage operation on UAVs that leads to high energy savings in both compute-level operation and systemlevel quality-of-flight. We perform extensive experiments on 72 autonomous navigation scenarios and demonstrate that BERRY generalizes well across environments, UAVs, autonomy policies, operating voltages and fault patterns, and consistently improves robustness, efficiency and mission performance, achieving up to 15.62% reduction in flight energy, 18.51% increase in the number of successful missions, and 3.43× processing energy reduction.

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A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC

Cited by 12 publications

References 10 publications

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge

Analyzing and Improving Resilience and Robustness of Autonomous Systems

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