A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application

Abstract

Voltage domain ADC architectures require high gain and high bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due to noise, small gain and lower overdrive voltage. Due to these limitations, the inclination shifted towards high-speed converters which don’t require opamps. Time based Analog to Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in the end. This work is concerned around the design of a high-resolution time to digital converter (TDC) and proposing a novel high-speed, low power consuming voltage to time converter (VTC) circuit. Both the circuits were implemented in Cadence Virtuoso EDA tool version 6.1.7 and Spectre was employed for running the simulations. TDC circuits had resolution of 13.425 ps and consume power of 1.873 μW. Process corner analysis and Monte Carlo analysis were performed on VTC design to determine worst possible deviations in performance. The proposed VTC exhibited delay of 23.79 ps with power consumption of 21.83 μW at 1 Volt. The presented TDC and VTC circuits can be used to design high-speed time-based Analog to Digital Converters.