A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Zhou, Dadian; Briseno-Vidrios, Carlos; Jiang, Junning; Park, Chulhyun; Liu, Qiyuan; Soenen, Eric; Kinyua, Martin; Silva-Martí­nez, J.

doi:10.1109/tcsi.2019.2925743

Cited by 15 publications

(3 citation statements)

References 29 publications

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“…ADC described by Zhou et al (2019) managed to improve the power consumption to less than 100 mW at 260 MS/s and has DNL error of 11 / À1 LSB, as compared to the work by Luo et al (2009) mentioned earlier. Zhou et al (2019) reused the bias current for the current-steering DAC and the linear OTA thus, less static current is consumed and becomes less noisy compared with the topology when the OTA and the DAC are biased separately. As for the work that has been done by Chu et al (2015), their ADC gives better power consumption, i.e.…”

Section: Introductionmentioning

confidence: 93%

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

Idros

Aziz

Rajendran

2020

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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Section: Introductionmentioning

confidence: 93%

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

Idros

Aziz

Rajendran

2020

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“…The ADC for quantization uses a singlebit quantizer because any complex element matching circuit does not require by the DAC and the ADC circuit is inherently linear. Moreover, owing to the configuration of only two DACs and one comparator without a calibration circuit, the total power consumption and the overall silicon area of the DAC and digital circuit are much lower than the multibit quantizer [24]. On the other hand, the noise specification for quantization requires the oversampling ratio and the ADC order to be defined.…”

Section: Implementation Of the Adc Circuitmentioning

confidence: 99%

A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors

Nebhen¹,

Ferreira²

2022

Computer Modeling in Engineering &Amp; Sciences

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This paper presents a proposed low-noise and high-sensitivity Internet of Thing (IoT) system based on an M&NEMS microphone. The IoT device consists of an M&NEMS resistive accelerometer associated with an electronic readout circuit, which is a silicon nanowire and a Continuous-Time (CT)ADC. The first integrator of the ADC is based on a positive feedback DC-gain enhancement two-stage amplifier due to its high linearity and low-noise operations. To mitigate both the offset and 1/f noise, a suggested delay-time chopper negative-R stabilization technique is applied around the first integrator. A 65-nm CMOS process implements the CT ADC. The supply voltage of the CMOS circuit is 1.2-V while 0.96-mW is the power consumption and 0.1-mm 2 is the silicon area. The M&NEMS microphone and ADC complete circuit are fabricated and measured. Over a working frequency bandwidth of 20-kHz, the measurement results of the proposed IoT system reach a signal to noise ratio (SNR) of 102.8-dB. Moreover, it has a measured dynamic range (DR) of 108-dB and a measured signal to noise and distortion ratio (SNDR) of 101.3-dB.

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“…This allows a scaling down of the capacitor in that stage. Other approaches employ current-reuse methods which reuse the bias current for the current-steering DAC and the linear OTA [9] and provide an overall bias current reduction. This architecture is employed however to compensate residue gain and nonlinearity errors.…”

Section: Introductionmentioning

confidence: 99%

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

Díaz‐Madrid

Doménech‐Asensi

Ruiz‐Merino

et al. 2020

Analog Integr Circ Sig Process

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This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier (OTA) is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.

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A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Cited by 15 publications

References 29 publications

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

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A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Cited by 15 publications

References 29 publications

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

Contact Info

Product

Resources

About

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier