2013
DOI: 10.1007/s10470-013-0050-x
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A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

Abstract: We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. I… Show more

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Cited by 6 publications
(2 citation statements)
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“…While the iTDS-1 used the ADC built in the MCU, the iTDS-2 has an on-chip 13-bit SAR ADC to reduce power consumption and loading effect on the AFE output stage. The SAR ADC operates at 1024 Hz and employs noise shaping and foreground digital calibration schemes, to decrease the digitization noise by pushing it out into a higher frequency band and to minimize the effects of capacitor mismatch, respectively [ 34 , 35 ]. For noise shaping, the residual charge at the end of each conversion process is delivered to the next conversion stage, using the switched capacitor connected in parallel to the capacitor bank [ 34 ].…”
Section: Design and Implementationmentioning
confidence: 99%
“…While the iTDS-1 used the ADC built in the MCU, the iTDS-2 has an on-chip 13-bit SAR ADC to reduce power consumption and loading effect on the AFE output stage. The SAR ADC operates at 1024 Hz and employs noise shaping and foreground digital calibration schemes, to decrease the digitization noise by pushing it out into a higher frequency band and to minimize the effects of capacitor mismatch, respectively [ 34 , 35 ]. For noise shaping, the residual charge at the end of each conversion process is delivered to the next conversion stage, using the switched capacitor connected in parallel to the capacitor bank [ 34 ].…”
Section: Design and Implementationmentioning
confidence: 99%
“…Due to the matching errors of internal components of the SAR ADC, it is widely used in medium and low speed and medium-resolution sensor networks. Although the SAR ADC [ 7 ] has power consumption efficiency, it is difficult to realize high precision due to its structural characteristics and requires additional correction circuits which increases the component overhead and power consumption of the ADC [ 8 ]. To combat with the above deficiencies, the core technologies of the sigma-delta modulator which are based on oversampling and noise shaping technologies were proposed to achieve high speed and high precision.…”
Section: Introductionmentioning
confidence: 99%