A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Abstract

Binary image descriptors, which derive image feature description from the local image patches directly, are widely adopted in the mobile and embedded applications due to lower computational complexity and memory requirement. With the aim of improving the computation efficiency without degrading recognition performance, a light-weight binary robust descriptor (L-BIRD) is proposed based on the analysis of the state-of-the-art binary descriptors in this paper. A directional edge detection and optimized keypoint score function are developed to refine the keypoints. In addition, rotation invariance is achieved by executing a circular symmetric based descriptor generation and a coarse-grained orientation calculation method concurrently. Experimental results demonstrate that the proposed keypoint detector and binary descriptor achieve more than 2 times speedup and at least 23.6% improvement in processing speed with comparable performance respectively. Furthermore, a VLSI architecture is also designed based on in-depth exploration of bit-level and task-level parallelism. Based on the post-layout simulation in TSMC 65 nm CMOS process, the accelerator can achieve 135 frames per second (fps) on 1080p image while only consuming 87.5 mW at 200 MHz operating frequency.

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“…Wenping et. al have designed a binarydescriptor-based image feature extraction accelerator [17]. The proposed accelerator is implemented in the Verilog hardware description language and verified on a FPGA platform.…”

“…There are many algorithms used in feature extraction with different characteristics and performances. Many algorithms such as scale-invariant feature transform (SIFT) , speeded up robust features (SURF) and histogramof-gradients-based (HoG) are computationally expensive and they require huge memory access and storage [11] [16] [17]. The binary descriptors are more computationally efficient and requires less memory [4] [13].…”

High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

“…This leads to over 17% reduction of the external memory bandwidth. Also, rather than using centroid-based orientation that leads to high computational complexity, the approach in [20] is adopted, which relies on the comparison of adjacent pixels on the Bresenham circle to determine the orientation. Their work mainly focused on the architecture for FAST and Non-Maximal Suppression (NMS).…”