A 14-b 150 MS/s CMOS DAC with Digital Background Calibration

Chen, Hsin-Hung; Lee, Jaesik; Weiner, Joe; Chen, Young-Kai; Chen, Jiunn-Tsair

doi:10.1109/vlsic.2006.1705307

Cited by 17 publications

(10 citation statements)

References 3 publications

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“…Both of the MSB and LSB blocks are coded with thermometer codes of 128 current cells in each block. The LSB current cell size is optimized and also randomly placed in order to eliminate the current mismatch [4]. The LSB block will not go through any trimming process in this chip.…”

Section: Fig 2 Pipeline Adc Architecturementioning

confidence: 99%

Digitally-assisted analog designs for submicron CMOS technology

Lai

Lin

Weng

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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Three different digitally-assisted analog designs are presented to demonstrate the powerful way to solve the analog design deficiencies in the submicron CMOS technology. A 200 MS/s 12-bit pipeline ADC is using the split-capacitor correlation method to solve the linear and nonlinear problems. A 1 GS/s 14-bit current-steering DAC is using the programmable sub-DAC to continuously trimming the current mismatches. A 25 MS/s 16-bit 6 6' ADC is using the adaptive way to correct the leakage noise and DAC nonlinearity.

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Section: Fig 2 Pipeline Adc Architecturementioning

confidence: 99%

Digitally-assisted analog designs for submicron CMOS technology

Lai

Lin

Weng

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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“…Further, most of the DAC are now fabricated with the technology of standard CMOS process to satisfy the condition of an Intellectual Property (IP) in a large CMOS SOC. There exist many kinds of design technique to implement a CMOS DAC such as a decoder based design with an operational amplifier, a current steering type design, a cyclic or a charge redistributed type design, and so on [1][2][3][4][5][6][7][8]. Among them, a current steering type design is widely used because it has the capability of driving resistive loads without any special buffers like operational amplifiers and it has the suitability for simple CMOS implementation.…”

Section: Introductionmentioning

confidence: 99%

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

Lee

Song

2014

Analog Integr Circ Sig Process

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A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 lm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 lW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.

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“…However, the most widely used design technique is the current steering type [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] because it has the capability of driving resistive loads without any special buffers, such as operational amplifiers, and is suitable for simple CMOS implementation. Further, it provides high-speed operation and its power consumption is low in comparison with the other types.…”

Section: Introductionmentioning

confidence: 99%

“…Through the symmetrical relocation of the current cells, many of the non-linearity errors were drastically improved. Thus, the symmetrical current cell relocation technique play an important role in designing current steering DACs [6][7][8]. However, the chip area is much increased due to the metal routing, even though the chip performance is improved due to the symmetrical cell relocation.…”

Section: Introductionmentioning

confidence: 99%

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

Moon

Song

Shin³

et al. 2009

Analog Integr Circ Sig Process

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A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 ? 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 lm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm 2 (510 9 510 lm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.

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A 14-b 150 MS/s CMOS DAC with Digital Background Calibration

Cited by 17 publications

References 3 publications

Digitally-assisted analog designs for submicron CMOS technology

Digitally-assisted analog designs for submicron CMOS technology

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

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