A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor

Bisiaux, Pierre; Lelandais-Perrault, Caroline; Kolar, Anthony; Bénabès, Philippe; Santos, Filipe Vinci dos

doi:10.1109/newcas.2017.8010144

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…In our proposed IADC, M = 2, OSR = 128 and N = 256 clock periods were chosen for converting an input sample. The SINC3 filter uses a novel implementation of the familiar Hogenauer structure [9], which contains a cascade of integrating, differentiating, and scaling stages.…”

Section: Decimation Filtermentioning

confidence: 99%

“…This paper shows a design methodology of a complete IADC for eight multiplexing channel. IADCs consist of an analog modulator followed by a digital low pass filter like conventional Σ∆ ADCs expect, it resets after each M number of cycles at the higher oversampling-ratio (OSR) of M [9]. In this proposed IADC circuity, the analogue modulator consists of an integrator, comparator and one-bit digital-to-analog convertor (DAC).…”

Section: Introductionmentioning

confidence: 99%

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10-Bit 200 kHz/8-Channel Incremental ADC for Biosensor Applications

Gupta¹,

Earnest²,

Mitra³

2022

J CIRCUIT SYST COMP

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In this paper, a second-order discrete-time (DT) modulator for 8-channel Incremental Sigma-Delta analog-to-digital converter (IADC) is presented for biomedical applications ranging from kHz. The proposed DT modulator with input bandwidth of 25[Formula: see text]kHz on each channel is sampled at 51.2[Formula: see text]MHz, with oversampling ratio of 128 implemented at 180[Formula: see text]nm technology. The proposed IADC has high resolution, multichannel A/D conversion, simple architecture, low offset, low gain error and low area over the standard ADCs available. Measured results show that the SNR, DR, ENOB, power consumption and chip area of the proposed IADC are 63.9[Formula: see text]dB, 62.2[Formula: see text]dB, 10.11 bits, 0.832[Formula: see text]mW and 0.032[Formula: see text]mm2, respectively, at 1.8V power supply. For testing purpose, the noncoherent sampling is done to get the FFT plot of the output signal. For further validation, the proposed second-order IADC was also designed and compared in MATLAB/Simulink.

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Section: Decimation Filtermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

10-Bit 200 kHz/8-Channel Incremental ADC for Biosensor Applications

Gupta¹,

Earnest²,

Mitra³

2022

J CIRCUIT SYST COMP

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“…In order to save area and power, we chose an inverter-based SC amplifier circuit [15,16]. This kind of amplifier suffers from low gain and high variability in the bias point.…”

Section: A Principle Of Operationmentioning

confidence: 99%

An Accuracy-Area Tradeoff for Mixed-Signal Computation in Programmable Smart Image Sensors

Hir

Santos

Kolar

2018

2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)

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Tightly embedded systems often require low power real time processing of acquired sensor data. This paper presents the design and transistor-level implementation of a mixed-signal processing element for highly area-constrained systems in applications where approximate computing is sufficient. The analog processing unit consists of a switched capacitor circuit whose imperfections such as finite gain or offset errors are evaluated here through theoretical analyses and Monte Carlo simulations for a CMOS 0.35μm technology. Transistor-level simulation results further demonstrate that this processing unit is suitable for image pre-processing tasks such as spatial convolution for edge detection.

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“…As an amplifier, an inverter is used because only low gain is needed and this saves area. An offset compensation scheme (capacitor C c ) is used to cancel the influence of the offset of the inverter which changes according to process [21,22]. Switch B allows for subtraction by reverse charging of the input, while switches E and F maintain the offset compensation.…”

Section: A Distributed Architecturementioning

confidence: 99%

Distributed mixed-signal architecture for programmable smart image sensors

Hir

Kolar

Santos

2018

Analog Integr Circ Sig Process

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Smart vision systems on a chip are promising for embedded applications. Currently, flexibility in the choice of integrated pre-processing tools is obtained at the expense of total silicon area and fill factor, which are otherwise optimized provided that the sensor performs a specific task. We propose a new architecture based on macropixel-level processing to improve the trade-off by using the same processing elements (PEs) for a whole group of pixels. In this paper, we show through transistor-level simulations the feasibility of using macropixel PEs. Their operative part is analog to avoid the bottleneck of analog to digital converters (ADC) and has digital control which is distributed in and out of the matrix of pixels. PEs are designed to be suitable for coefficient-reconfigurable spatial and temporal filtering. Sharing electronics among several pixels and matching existing algorithms to the target architecture allow for such programmability without degrading too much pixel area nor fill factor.

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A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor

Cited by 5 publications

References 12 publications

10-Bit 200 kHz/8-Channel Incremental ADC for Biosensor Applications

10-Bit 200 kHz/8-Channel Incremental ADC for Biosensor Applications

An Accuracy-Area Tradeoff for Mixed-Signal Computation in Programmable Smart Image Sensors

Distributed mixed-signal architecture for programmable smart image sensors

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