A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration

Ali, Ahmed; Dinc, Huseyin; Bhoraskar, Paritosh; Dillon, Chris; Puckett, Scott; Gray, Bryce; Speir, Carroll; Lanford, Jonathan; Brunsilius, Janet; Derounian, Peter; Jeffries, Brad; Mehta, Ushma; McShea, Matthew; Stop, Russell

doi:10.1109/jssc.2014.2361339

Cited by 154 publications

(39 citation statements)

References 8 publications

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“…Designing an op-amp with this unity gain bandwidth is a non-trivial design and consumes a lot of power. A recent pipelined ADC [21] with an op-amp with similar specs requires a 2.5V op-amp supply. This sets an upper bound on for this technology, hence the choice of the value of _ .…”

Section: Appendixmentioning

confidence: 99%

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

O’Hare¹,

Scanlan

Thompson

et al. 2018

IEEE Trans. VLSI Syst.

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Section: Appendixmentioning

confidence: 99%

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

O’Hare¹,

Scanlan

Thompson

et al. 2018

IEEE Trans. VLSI Syst.

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“…One is the signal dependent parasitic capacitance from input to ac ground during the track phase, represented by the variable capacitor C p1 . This voltage-dependent capacitor C p1 causes a nonlinear charging current, which creates a nonlinear voltage error by traveling through the ADC equivalent driving impedance R s [1], [17], thus degrading the tracking linearity and sampling precision. Considering the fact that this error originates from a current charging a capacitance, it becomes proportionately larger with frequency increasing.…”

Section: S/h Parasitic Optimizationmentioning

confidence: 99%

“…Benefiting from the IF/RF sampling ability, the architecture of cellular base stations evolves from multi-narrowband receivers to a single wideband multi-channel receiver, which transfers the major work of individual channel extraction to mature digital signal processing and hence significantly reduces the cost and complexity of cellular base stations [1]- [4]. Other applications such as cable modems, CCD medical imaging, and computed tomography scanners have similar quantization requirements [3], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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“…The requirement of BW in Long-Term-Evolution Advanced (LTE-A) communication standard has risen to 100 MHz. Nyquist ADCs, typically pipeline ADCs [1,2], have been used in macro base stations for their high BW. However, indispensable input buffers for driving thermal-noiselimited switched input capacitors and anti-aliasing filter cause significant power consumption and design complexity.…”

Section: Introductionmentioning

confidence: 99%

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Xiao

Ren

et al. 2020

Nanoscale Res Lett

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The bandwidth of a modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.

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A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration

Cited by 154 publications

References 8 publications

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

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