A 14-megapixel 36 x 24-mm²image sensor

Abstract

We will present a 3044 x 4556 pixels CMOS image sensor with a pixel array of 36 x 24 mm 2 , equal to the size of 35 mm film. Though primarily developed for digital photography, the compatibility of the device with standard optics for film cameras makes the device also attractive for machine vision applications as well as many scientific and highresolution applications. The sensor makes use of a standard rolling shutter 3-transistor active pixel in standard 0.35 µm CMOS technology. On-chip double sampling is used to reduce fixed pattern noise. The pixel is 8 µm large, has 60,000 electrons full well charge and a conversion gain of 18.5 µV/electron. The product of quantum efficiency and fill factor of the monochrome device is 40%. Temporal noise is 35 electrons, offering a dynamic range of 65.4 dB. Dark current is 4.2 mV/s at 30 degrees C. Fixed pattern noise is less than 1.5 mV RMS over the entire focal plane and less than 1 mV RMS in local windows of 32 x 32 pixels. The sensor is read out over 4 parallel outputs at 15 MHz each, offering 3.2 images/second. The device runs at 3.3 V and consumes 200 mW.

A 0.5 MP, 3D-Stacked, Voltage-Domain Global Shutter Image Sensor with NIR QE Enhancement, Event Detection Modes, and 90 dB Dynamic Range

“…The thick last metal in particular made an impressive difference in power distribution across the narrow row driver area. Due to that, we were able to reduce the width of the row driver by more than 10 times compared to our previous sensors using traditional frontside-illuminated (FSI) technology [3,[11][12][13]. Additionally, we split the row driver into two parts (left and right of the array) to further reduce its width and to have a more symmetrical placement of the readout blocks.…”

“…The column bias circuitry was placed in the pixel silicon layer to spare the logic silicon area and to improve the noise performance. The traditional column sample and hold circuitry [11] were removed to reduce the area and improve noise performance, with column analog The simplified circuitry of the analog readout part is depicted in Figure 5. The column bias circuitry was placed in the pixel silicon layer to spare the logic silicon area and to improve the noise performance.…”

“…The column bias circuitry was placed in the pixel silicon layer to spare the logic silicon area and to improve the noise performance. The traditional column sample and hold circuitry [11] were removed to reduce the area and improve noise performance, with column analog and digital correlated double sampling operations performed directly in the ramp ADC.…”

Roadmap for CMOS image sensors: Moore meets Planck and Sommerfeld

“…Even high-quality imaging applications that traditionally use charge-coupled device (CCD) imagers, such as single lens reflex (SLR) cameras, are increasingly equipped with high spatial resolution CMOS image sensors. 1 In part, the improved image quality is due to increased pixel density that is built on Moore's law: Over the past 25 years, the minimum lithographic feature size has decreased by thirty percent every three years. 2,3 CMOS technology scaling can improve image sensor performance in a variety of ways.…”