2016
DOI: 10.1109/jssc.2015.2456873
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A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

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Cited by 18 publications
(1 citation statement)
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“…We show the published cell size for all technologies discussed above in figure 1(c), i.e. SRAM [46][47][48][49][50][51][52][53], eDRAM [54][55][56][57][58][59], eFlash [60][61][62][63][64][65][66][67], DRAM [41,68], eReRAM [69][70][71][72][73], STT-MRAM [42,[74][75][76][77][78][79][80][81][82][83][84][85][86][87]. Note that the SRAM cell sizes down to 7 nm are from literature while the cell sizes (F 2 ) for 3 and 5 nm are linear extrapolation based on the cell sizes from 22 nm to 7 nm.…”
Section: Scaling Analysismentioning
confidence: 99%
“…We show the published cell size for all technologies discussed above in figure 1(c), i.e. SRAM [46][47][48][49][50][51][52][53], eDRAM [54][55][56][57][58][59], eFlash [60][61][62][63][64][65][66][67], DRAM [41,68], eReRAM [69][70][71][72][73], STT-MRAM [42,[74][75][76][77][78][79][80][81][82][83][84][85][86][87]. Note that the SRAM cell sizes down to 7 nm are from literature while the cell sizes (F 2 ) for 3 and 5 nm are linear extrapolation based on the cell sizes from 22 nm to 7 nm.…”
Section: Scaling Analysismentioning
confidence: 99%