A 14 ns 256 K*1 CMOS SRAM with multiple test modes

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

“…The second approach [23][24][25][26][27][28][29][30], uses extra hardware to partition the whole memory into small blocks and test them in parallel (using external test generation). Jarwala and Pradhan [25], showed that using partitioning methods, a significant saving in the test time can be achieved for large memories.…”