A 140-μW Front-End With 5.7-dB NF and +10-dBm OOB-IIP3 Using Voltage-Mode Boosting Mixer

Mohammadpour, Amin; Manstretta, Danilo; Castello, R.

doi:10.1109/lmwc.2021.3066420

Cited by 4 publications

(3 citation statements)

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“…More recently the same idea was reported in [71], which includes the BB stage, and achieves 20−24 dBm OOB IIP3 while burning only 1.7−2.5 mW in the 1.8−2.8 GHz frequency range. Another example of capacitive stacking MFRX is reported in [53]. It shows NF of 5.7dB with OOB-IIP3 of 10 dBm.…”

Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 99%

“…SAW-less RX architectures were already explored in [49] and will not be discussed extensively here. Recently, passive voltage mode boosting using capacitive stacking is emerging as an interesting way to make low NF MFRX with high linearity while consuming sub-mW power [52]- [53]. For instance, [52] shows an outstanding OOB-IIP3 of 25dBm while consuming 600 μW at 1GHz carrier frequency.…”

Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 99%

“…Here, to reduce chip area and to lower power consumption below 140 μW, a ring oscillator was used instead of an LC VCO. The drawback of this choice is that the NF will be substantially degraded in the presence of blockers due to the higher phase noise of the ring oscillator [53].…”

Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 99%

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Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Kargaran

Manstretta

Castello

2021

IEEE Open J. Solid-State Circuits Soc.

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Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phasetracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm 2 and consumes only 350 μW from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.INDEX TERMS Ultra low-power (ULP), current reuse, gm-boosting, complex filter, IoT, ultra-low-voltage (ULV).

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Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 99%