A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

“…The other approach for digital background full calibration [4,5] is based on the additive error code concept [17].…”

“…In [4], the digital coefficients f i are estimated splitting each sampling capacitor C S i in P parts (C S i ¼ P P n¼1 c S i;n ) considering an additive modulation scheme and two measurements per section C S i;n . The main drawbacks of this technique, in addition to the extra switches and parasites due to the sampling capacitor splitting, stem from: (a) the input dynamic range limitation and the increment of amplifier output requirements due to the analogue additive modulation term, and (b) the huge number of measurements required for the error code computation (in total 2PM estimations).…”

“…In total, this novel calibration approach considers only (P + M -1) measurements with the consequent advantages in term of memory resources and convergence time with respect to the original works in [4,18], specially for high resolution stages. Additionally, the proposed swapping algorithm requires minimum modifications on the high sensitive analogue building blocks (capacitor splitting is only performed on the reference device), it avoids the input dynamic range limitation, it does not introduce additional output swing requirements and, as described in the following sub-section, the calibration hardware (basically, an accumulator and one small register bank) can be in part shared with the digital logic for the characterisation of the reference device [18].…”

“…Among these techniques, correlation-based approaches [4][5][6][7][8][9][10][11][12][13][14][15] are the particular interest as they can obtain an estimation of the ADC errors, with minimum impact on the critical analogue components and low-cost calibration logic, introducing a digital modulation sequence in the stage transfer characteristic (usually a pseudo-random number). These methods perform a full calibration of the amplifier finite DC-gain and capacitor mismatch non-linearity using a single algorithm [4,5]; or considering independent methods for the estimation of both the interstage gain [7][8][9][10][11] and the MDAC non-linear errors [12][13][14][15]. 1 In any case, the above adaptive techniques can calibrate the ADC errors without interrupting the input conversion, and therefore, being suitable for background applications.…”

“…These benefits are specially relevant in the case of [4], as it allows: (1) the relaxation of the analogue blocks specifications, (2) the elimination of the input dynamic range limitation and the increment of amplifier output requirements due to the analogue additive modulation, and (3) a drastic reduction of the number of measurements in high resolution stages avoiding the exponential dependence on the stage resolution.…”