A 15-bit, 5 MSPS SAR ADC with on-chip digital calibration

Abstract

In this paper, a digital algorithm based on a 15-bit, 5 million samples per second (MSPS), high-speed successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It features on comparator offset cancellation and capacitor mismatch calibration. The algorithm uses a 13-bit bypass array to measure the errors of both comparator and capacitors. During calibration, errors are read and put into the bypass array to compensate for the mismatches of the main array. Verified by MATLAB, the errors of the SAR ADC output can be corrected into 1 LSB with the help of calibration. The simulation results show that the proposed algorithm improves the precision of the SAR ADC significantly.