A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

Zhang, Xiaowei; Qian, Fu-Yue; Xi, Jian-Xiong; Wang, Tao; He, Lenian

doi:10.1016/j.mejo.2022.105618

Cited by 6 publications

(1 citation statement)

References 25 publications

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“…ADC designs that optimize power consumption without sacrificing performance are therefore crucial [2]. Performance parameters are crucial in the case of a 16-bit, 500 MS/s successive approximation register ADC (SAR-ADC) that is developed at a 45-nm CMOS technology by Cadence Virtuoso, especially for low power applications [3]. With the help of important metrics like the signal-to-noise and distortion ratio (SNDR), figure of merit (FOM), and total harmonic distortion (THD) this review tries to assess the ADC's performance by MATLAB for post-simulation [4].…”

Section: Introductionmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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Section: Introductionmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

View full text Add to dashboard Cite

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A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

Zhang,

Xin,

Tong

2023

Microelectronics Journal

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A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

Wang,

Liang,

Zhang

et al. 2024

Microelectronics Journal

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A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

Cited by 6 publications

References 25 publications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

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A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

Cited by 6 publications

References 25 publications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications

A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

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Resources

About

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications