A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified Gdi Cells for Low Power and Area Constraints

Abstract

Abstract:The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the UrdhvaTiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.