A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

Abstract

A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

“…Table 1 summarizes the performance comparison of the proposed SBT with the state-of-the-art full-duplex transceivers over on-chip interconnects. Thanks to the proposed SBT, the maximum achievable data rate is doubled with respect to Wary and Mandal 32 and improved by 25% in comparison with Ebrahimi Jarihani et al 33 Therefore, the proposed solution has the highest data rate (20 Gbps) among the previously reported FDTs while consuming comparable power. [28][29][30][31][32][33] The design reported in Wary and Mandal 32 is superior in terms of energy-efficiency while this solution offers a lower data-rate of 10 Gbps.…”

“…Thanks to the proposed SBT, the maximum achievable data rate is doubled with respect to Wary and Mandal 32 and improved by 25% in comparison with Ebrahimi Jarihani et al 33 Therefore, the proposed solution has the highest data rate (20 Gbps) among the previously reported FDTs while consuming comparable power. [28][29][30][31][32][33] The design reported in Wary and Mandal 32 is superior in terms of energy-efficiency while this solution offers a lower data-rate of 10 Gbps. It can be imagined that the performance of the solution described in 28 will be degraded by using longer on-chip interconnections.…”

“…Lately, SBTs have been presented over on-chip interconnections. [27][28][29][30][31][32][33] A current-mode SBS for on-chip interconnection is studied in Huang et al, 27 which has overall poor performance. The authors are presented a current-mode differential SBT in Huang et al 28 by utilizing an adaptive impedance-matching structure.…”

“…In this paper, an alternative solution is proposed to overcome the problems in the attainment of high-speed FDTs over the on-chip interconnections and improve the performance of the previously reported SBT in Ebrahimi Jarihani et al 33 A transistor is utilized as a hybrid device to employ the impedance-matching at both sides of the on-chip interconnection, separating the transmitting and the incoming signals and also carrying out voltage-mode echo cancelation with the assistance of an auxiliary and a main drivers. In addition, using the compensation capacitance (C c ) in 33 not only creates the similar loading effects in the presented topology for better echo cancelation in voltage-mode but also lowers the overall bandwidth of the system and limits the maximum achievable data-rate to 16 Gbps at full-duplex operation. Nevertheless, the presented topology 33 is incapable to eliminate the high-frequency components of the selfinerface signal which appears as spikes in the middle of the received data (due to the propagation delay of the interconnect) coming from tranceiver in the other end of the interconnect.…”

“…In addition, using the compensation capacitance (C c ) in 33 not only creates the similar loading effects in the presented topology for better echo cancelation in voltage-mode but also lowers the overall bandwidth of the system and limits the maximum achievable data-rate to 16 Gbps at full-duplex operation. Nevertheless, the presented topology 33 is incapable to eliminate the high-frequency components of the selfinerface signal which appears as spikes in the middle of the received data (due to the propagation delay of the interconnect) coming from tranceiver in the other end of the interconnect. In the proposed SBT, a RChigh-pass filter (HPF) is utilized as a differentiator to eliminate residual echo by generation cancelation current and perform better echocancelation by the incorporation of a hybrid device.…”