A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell

Sasaki, K.; Ueda, Kazuhiro; Takasugi, Kashiya; Toyoshima, Hideo; Ishibashi, Koji; Yamanaka, Toshiaki; Hashimoto, Norikazu; Ohki, N.

doi:10.1109/4.245592

Cited by 13 publications

(3 citation statements)

References 3 publications

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“…The array standby current for the BTL SRAM is given by ISTBY = IMAX x NCELLS @VCB 1 5.5V (4) where NCELLS is the SRAM density.…”

Section: Btl Sram Cell Operationmentioning

confidence: 99%

“…The 4-T poly-load cell requires a dedicated process flow to preserve the super-high-resistivity poly (Giga-Tera ohmcm range) [3]. The TFT approach requires an addition of two poly layers [4]. As a result, for embedded applications, it is imperative to develop a dense SRAM concept that can be easily integrated into a standard CMOS process, ideally, in the form of an SRAM add-on module.…”

Section: Introductionmentioning

confidence: 99%

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A bipolar load CMOS SRAM cell for embedded applications

Shubat¹,

Kazerounian²,

Irani³

et al. 1995

IEEE Electron Device Lett.

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This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 IL m2 with typical 0.8 p m design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps.

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“…The array standby current for the BTL SRAM is given by ISTBY = IMAX x NCELLS @VCB 1 5.5V (4) where NCELLS is the SRAM density.…”

Section: Btl Sram Cell Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A bipolar load CMOS SRAM cell for embedded applications

Shubat¹,

Kazerounian²,

Irani³

et al. 1995

IEEE Electron Device Lett.

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“…In the past, we have applied current mode techniques to the implementation of bidirectional associative memories (BAM) ( [4,5]). These small chips proved that current mode techniques such as the clamped bit-line architecture now standard in SRAMs ( [22,23]) and WTA circuits are useful in the design of larger size chips.…”

Section: Circuits and Design Methodologymentioning

confidence: 99%

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

Pouliquen¹,

Andreou²,

Strohbehn³

The Springer International Series in Engineering and Computer Science

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Sram Chips

Carns¹,

Zheng²,

Wang³

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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The sections in this article are The Basics of Memory Operation The Fundamental Components of the Sram Cell Inverter Analysis and Comparison The Fundamental Components of the Basic Sram Architecture Improving Today'S Sram Cell Cost and Performance Application‐Specific Sramss Sram Testing and Reliability Novel Sram Cell Configurations for Future High‐Speed/High‐Density Applications

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A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell

Cited by 13 publications

References 3 publications

A bipolar load CMOS SRAM cell for embedded applications

A bipolar load CMOS SRAM cell for embedded applications

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

Sram Chips

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