A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder

Wang, Chua‐Chin; Jose, Oliver Lexter July A.; Yang, Wen-Jen; Sangalang, Ralph Gerard B.; Tolentino, Lean Karlo S.; Lee, Tzung-Je

doi:10.1007/s00034-022-02212-2

Cited by 3 publications

(2 citation statements)

References 36 publications

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“…Wang, Jose [24] proposed the implementation of an 8-bit CLA circuit via all-n-transistor logic, with a clock frequency of 800 MHz and power consumption of 28.8 mW. This circuit was successfully fabricated on a chip.…”

Section: Literature Reviewmentioning

confidence: 99%

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

Ahmadpour,

Jafari Navimipour

2023

Phys. Scr.

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There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

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Section: Literature Reviewmentioning

confidence: 99%

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

Ahmadpour,

Jafari Navimipour

2023

Phys. Scr.

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“…The suggested adder-subtractor module provides 2-bit ternary numbers with addition and subtraction [20]- [23]. The module accomplishes operations using the symmetry idea in a ternary adder and the structure of a subtractor from a popular ternary adder module [24], [25]. This cell's logical execution level can be found in…”

Section: Adder Subtractor Modulementioning

confidence: 99%

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

Krishna Peddachowdappa,

Vardhan

2023

IJEECS

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<span>The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, communication systems, and so on. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ.</span>

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An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

Battini,

Kosaraju

2024

Semicond. Sci. Technol.

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To choose the option between an excess-1 result and a normal result,the conventional carry select adder (CCSA) employs two ripple-carry adders and amultiplexer in the last step. Second, whereas the proposed single-stage carry selectadder (SSCSA) avoids using full adders for the generation of both normal and excessresults, the present full adders require multiple full adders. A novel architecture isdeveloped and specifically designed to improve power dissipation and latency. It relieson a single circuit that produces normal/excess-1 results dependent on input carry.Heterogeneous logic combining CMOS, Dual Value Logic (DVAL), and TransmissionGate Logic (TRGL) with 22nm Fin-FETs powers the 1-bit SSCSA circuit. Bettercircuit regularity is displayed by the 4-bit SSCSA as it only uses one type of 1-bitSSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22nm FinFETtechnology, all adders, including 4- and 8-bit adders, are designed, simulated, andexamined. According to the resulting study, the 4-bit SSCSA outperforms the bestadder currently in use in terms of speed performance and power dissipation by 17.6%and 27.6%, respectively. By comparison with all other designs, SSCSAs outperformthem at each and every corner.

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A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder

Cited by 3 publications

References 36 publications

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

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