A 16-µW 10-kHz BW incremental <i>ΔΣ</i> ADC with automatic EDO canceling for implantable neural recording

Abstract

This paper presents a DC-coupled, incremental ΔΣ analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural signal recording. To address the problem of electrode DC offset (EDO), a compensation circuit is proposed in this paper which can automatically cancel the EDO. Fabricated in a 180-nm CMOS process, the prototype ADC achieves a high input impedance, 20-mVpp linear input range, 60.3-dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 16 𝜇W and an area of 0.0165𝑚𝑚 2 .The referedto-input (RTI) noise is 6 𝜇Vrms (1-10kHz) and it can cancel the EDO up to ±90𝑚𝑉 .

A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

“…The remaining sections of this paper are organ as follows: Section 2 provides a mathematical analysis of the working principle of A However, as the number of integrated channels increases, the first approach becomes limited by the complex signal processing chain, which restricts the area of the recording unit circuit. To address this issue, researchers have proposed a second solution, as shown in Figure 1b, which directly quantifies neural signals using low-noise ADC [24][25][26][27][28][29][30][31][32]. These ADCs are mostly oversampling-type ADCs, utilizing noise shaping to improve accuracy.…”

“…Refs. [28][29][30] utilized an incremental ∆Σ ADC architecture. The area of the recording unit in [28,29] is very small: less than 0.005 mm 2 .…”