A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Chun, Ki Chul; Yong-Gyu, Chu; Heo, Jeong Wook; Kim, Taesung; Kim, Soo-Hwan; Yang, Hak-Cheol; Kim, Mi-Jo; Lee, Chang-Kyo; Kim, Juhwan; Hyunchul, Yoon; Shin, Chang-Ho; Cha, Seung-Do; Kim, Hyungjin; Kim, Young‐Sik; Kim, Kyungryun; Kim, Young‐Ju; Choi, Won-Jun; Yim, Dae-Sik; Lee, Jun-Ha; Choi, Young; Kwon, Yong-Min; Choi, Seong Hee; Kim, Jung-Wook; Park, Yoon-Suk; Kang, Woongdae; Chung, Jihoon; Kim, Seung Hyun; Ryu, Yesin; Cho, Seong-Jin; Shin, Ho-Jun; Jung, Hae-Min; Kwon, Sanghyuk; Kang, Kyuchang; Lee, Jongmyung; Song, Yujung; Kim, Young-Jae; Kim, Eunah; Ha, Kwang Soon; Kim, Kyoungho; Hyun, Seok-Hun; Ko, Seungbum; Choi, Jung-Hwan; Sohn, Young-Soo; Park, Kwang-Il; Jang, Seong-Jin

doi:10.1109/isscc.2018.8310256

Cited by 15 publications

(5 citation statements)

References 3 publications

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“…Recently, DRAM vendors introduced O-ECC to LPDDR4, DDR5, and HBM2E [16]- [18]. These architectures add extra cells to the core and encoding/decoding circuitry to the bank or bank group [17], [19], [20]. Some implementations use 8-bit redundancy over 128-bit data to provide Single Error Correction (SEC) capability [19], [20].…”

Section: Error Correction Code (Ecc)mentioning

confidence: 99%

“…These architectures add extra cells to the core and encoding/decoding circuitry to the bank or bank group [17], [19], [20]. Some implementations use 8-bit redundancy over 128-bit data to provide Single Error Correction (SEC) capability [19], [20]. They use a larger codeword (128-bit data) than DRAM access granularity (64bit data) to amortize the redundancy down to 6.25%.…”

Section: Error Correction Code (Ecc)mentioning

confidence: 99%

“…With O-ECC, a DRAM device can correct errors internally and maintain its external reliability level. Current DDR5 makes use of 6.25% extra cells to provide the weak protection of Single Error Correction (SEC) over a 128-bit data block [19], [20].…”

Section: Introductionmentioning

confidence: 99%

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On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

Park

Kim

2022

IEEE Access

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As process scaling continues, DRAM is getting more vulnerable to errors. System companies and DRAM vendors have introduced ECC to protect DRAM against growing errors. ECC, however, should be combined with a repair mechanism to prevent non-transient faults from repeatedly producing errors and to prevent overlapping faults from accumulating into more severe errors. We propose a novel approach to repair memory and improve reliability with minimal overheads. On-die Dynamic Remapping Cache (DRC) minimizes the repair overheads by focusing on active faults. Most intermittent faults (e.g., Variable Retention Time) generate errors occasionally, and the number of active faults at any one time is significantly lower than the total. DRC tracks the activity and severity of faults at run-time and uses a small cache inside a DRAM to remap active faults. This efficiency enables aggressive remapping of bit faults, which eliminates fault accumulations and improves reliability. Our evaluation shows DRC can provide much stronger protection than the state-of-the-art protection schemes with no performance degradation and a negligible chip area overhead.

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Section: Error Correction Code (Ecc)mentioning

confidence: 99%

Section: Error Correction Code (Ecc)mentioning

confidence: 99%

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On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

Park

Kim

2022

IEEE Access

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“…Therefore, DRAM researchers and producers studied the placement of ECCs on DRAM dies, which are called inmemory ECCs [16], [17], [18]. Despite many difficulties in applying in-memory ECCs to DRAM [17], results have been reported for DRAM chips with in-memory ECCs [19], [20], [21].…”

Section: Introductionmentioning

confidence: 99%

“…According to the line-based replacement policy, one line spare must be used to repair a single fault, whereas an in-memory ECC can repair any number of single faults. Because of these features, the inmemory ECC is a technology proposed to correct soft errors occurring during operation; nevertheless, its use for improving yield is also a major goal [13], [16], [19], [20], [22], [23].…”

Section: Introductionmentioning

confidence: 99%

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

Han

Lee

et al. 2021

IEEE Access

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Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

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A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation

Kim

Yoon

Song

et al. 2022

2022 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Cited by 15 publications

References 3 publications

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

On-Die Dynamic Remapping Cache: Strong and Independent Protection Against Intermittent Faults

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation

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